OpenSPARC T1 Version 1.5 Released

Written by Administrator

Tuesday, 14 August 2007

New Features in the Release 1.5 of OpenSPARC T1

Within this release for the first time, there is support for an OpenSPARC T1 FPGA system with UART and DRAM controllers. It also supports the entire Xilinx tool chain for building new FPGA systems using OpenSPARC T1.

On this platform, you can map single thread T1, add right peripherals and then boot Hypervisor. You can also run standalone C program without the OS. Complete documentation and an entire new verification environment are also included as part of this release.

These new features are designed to enable a user to build real systems using the OpenSPARC T1 core. For further details on Xilinx, please refer to the Xilinx University program and information on the ml410 board.

Watch the video demonstration below and Download it!

Features of Version 1.5

Script support for FPGA synthesis with Xilinx SynthesisTechnology (XST).
An EDK project which permits the user to do the following things:

Download a single OpenSPARCT1 core and infrastructure needed to support it to a Xilinx FPGA.
Run SPARC diagnostic tests on the core.
Boot hypervisor on the core. Run a stand-alone program under hypervisor. (Should also be possible to boot an operating system under hypervisor as well).
Run a system-level simulation of the OpenSPARCT1 core executing in the FPGA system.

Release Notes for Release of Version 1.5

Running a full regression on the FPGA is very cumbersome. The sims script creates diag directory names which include the ":" character. The FPGA regression scripts copy the directory names exactly, which means that to run the command, the user has to use the escape sequence for that character.
In the documentation, The * OpenSPARC T1 Design and Verification Guide*, section 6.3.3, the sample command to run on the FPGA looks like this:

xtclsh edk-project-dir/chipscope_tcl/rundiags.tcl -edk edkproject-dir -list edk-project-dir/scripts/diag_mini.list -mode {core1:thread1_full:0 core1:thread1_mini:0}

It should read:

xtclsh edk-project-dir/chipscope_tcl/rundiags.tcl -edk edkproject-dir -list edk-project-dir/scripts/diag_mini.list -mode {core1%3Athread1_full%3A0 core1%3Athread1_mini%3A0}

A future fix will be to eliminate the ":" character from the directory names.
The TestApp_Memory application to the FPGA may not download to the FPGA. The user may see an error message like this:

Error(1060) D-Side Memory Access check failed

We are looking into it.
The copyright insertion script does not work properly for Perl or shell scripts. In these scripts, the first line is supposed to be a "#!" to indicate what type of script it is, and which program to execute it. The copyright header is inserted at the beginning of the file, even before this "#!" line. It needs to be inserted after the first line if the first line contains a "#!".

As a result, the following two Perl scripts will not have the proper copyright headers:

design/sys/edk/boardsim/bin2ascii.pl

design/sys/edk/scripts/genmemimage.pl
Most files in the archive have not write permissions. To run EDK, we recommend that the user adds write permissions to all files.
The full-system simulation script simulates for 7ms. However, the test does not end until around 7.5ms. The user can finish the simulation by typing "run 500us" at the prompt.