OpenSPARC T2 HW 1.3 Released

The OpenSPARC T2 processor is based on the UltraSPARC T2 processor, the world's fastest commodity processor with eight cores and eight threads per core.

New Features in HW Release 1.3

A fully synthesizable, reduced footprint, System-level model has been developed, suitable for FPGA and Emulation Platforms. This model has single OpenSPARC T2 core, crossbar interconnect, and WISHBONE Memory Controller ( from www.opencores.org). This environment supports RTL Simulation, FPGA Synthesis and Gate-level simulation with a one-to-one correspondence (i.e a given test runs unchanged in the RTL & Gate environments.) This environment is hardware platform neutral and can be ported on any FPGA prototyping board.

Specifically, following new flows are supported with this release:

• Added design compile-time flag 'FPGA'. Inclusion of this flag at the simulation or compile time will make design synthesizable with the FPGA tools. We have primarily tested this with Synplicity tool chain
• Added new regression environment in "sims" which allows full-system (core, crossbar, wishbone, memory controller) to be simulated in software.
• FPGA synthesis script 'fpga_synth' is provided to automate the synthesis of the design on FPGAs. Script is general enough to be used with any FPGA device or any vendor synthesis tool
• Finally, FPGA netlist simulation environment is provided to verify the functionality of the FPGA netlist

New Features in SW Release 1.2

• Added hypervisor/reset support and machine description files for the dual-core OpenSPARC T1 FPGA system. The clock frequency in single core machine description files has been increased.
• No other changes have been made.