OpenSPARC T2 SW 1.2 Released |
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The OpenSPARC T2 processor is
based on the UltraSPARC T2 processor, the world's fastest
commodity processor with eight cores and eight threads per core.
New Features in HW Release 1.2
In
the 1.0 release of the OpenSPARC T2, we had to remove two critical IO
interface design files - PCI-express and 10G Ethernet - to comply with
some of the legal restrictions. To provide OpenSPARC users alternative
means to simulate the entire T2 system-on-chip (SoC) functionality, Sun
has developed behavioral models for these two design blocks. These
models have similar functionality as the original RTL but are written
in the SystemC language. This release, for the first time, allows users
to simulate OpenSPARC T2 design with all the IO interfaces of the chip
including PCIe and 10G Ethernet. We have also augmented the
verification environment, test bench, and test vectors so that users
can verify the current design as well as any new variant of it.
Since
OpenSPARC T2's PCI-express functionality only supports root-complex
configuration, users would need to have access to Denali PureSpec
PCI-express model to exercise this model.
Finally,
we added one missing piece (64-bit Vector.so library) that would allow
OpenSPARC T2 simulation to run under 64-bit Linux operating system
which was missing earlier. With this piece in place, T2 simulation can
now be run both on 32b as well as 64b Linux platforms on x86 hardware.
New Features in SW Release 1.2
- Added hypervisor/reset support and machine description files for the dual-core OpenSPARC T1 FPGA system.
The clock frequency in single core machine description files has been increased.
- No other changes have been made.
Download HW and SW Release 1.2
and OpenSPARC T2 specifications
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