OpenSPARC T1 HW 1.7 Released

Release Notes for OpenSPARC T1 HW Version 1.7

1. Xilinx FPGA support for Virtex 5 FPGAs
   1. EDK and ISE Version 10.1 support
   2. EDK project for OpenSPARC Development Kit (ML505-V5LX110T board)
   3. Pre-synthesized 4-thread core netlist
   4. BEE3 Support
2. Support for a dual-core system using two OpenSPARC development boards
   1. Boards are connected through the SATA connectors on the board.
   2. Xilinx Aurora interface provides the communication protocol.
   1. Support for OpenSolaris Operating System boot
   2. Hypervisor support for 1-thread and 4-thread cores
   3. Minimal OpenSolaris RAM disk image.
   4. Sample ACE file provided to allow out-of-the box booting of OpenSolaris
   5. Support for bootins on two-core (two-board) system.
3. Support for Ubuntu Linux boot
4. Improved CCX Firmware code
   The memory subsystem is emulated using a MicroBlaze core. Here are the improvements that have been made to this code:
   1. Support for two-core systems
   2. Support for BEE3 platform
5. Improved performance when running regressions of diagnostic tests
   1. The procedure for running regressions of diagnostic tests was
      changed so that the tests do more initialization. As a result, it is no longer necessary to reprogram the FPGA between tests.
6. Miscellaneous Improvements
   1. Several scripts have been re-written to improve the user interface.
   2. Documentation has been updated and improved.

Issues

1. Floating-point support in Firmware
   Currently, the CCX firmware emulates the floating-point processing for the floating-point unit, because that unit is not included in the FPGA project. Approximately 50 diagnostic tests in the core1_full regression which exercise the floating-point unit fail when run on the FPGA project. The cause is probably due to the emulation code not supporting some special cases. These cases have been commented out of the core1_full test list.
2. EDK project workarounds
   Before running EDK on any of the project files supplied, the user must run the following script:
   
   $DV_ROOT/design/sys/edk/fix_edk.pl
   
   This script applies work-arounds for two problems encountered in EDK. Files from the EDK release area are copied to the project and modified.
3. Meeting Timing with other netlists. The EDK project comes with a pre-synthesized netlist for the OpenSPARC T1 core. This netlist was compiled with Synplify Pro, version 8.8, targeting the XC5VLX110 FPGA. With this netlist is used, both the dual-core project and the single- core project get through place & route with no timing violations. The two bit files included in the $DV_ROOT/design/sys/edk/bitfiles directory were implemented using this netlist.
   If Synplicity Pro is used targeting the XC5VXL110T (the actual part on the board), the dual-core design implements with no timing violations, but the single-core design has one small timing violation. It is a violation of a cross clock domain path. However, this timing violation didn't seem to affect the functionality of the design. We were still able to run a complete regression on this design with no failures.
   
   OpenSPARC T1 Netlists generated with XST version 10.1 were also tested. The dual-core design implemented with no timing violations, but the single-core design had a large timing violation. This can be corrected by changing the options specified in the file.
   $DV_ROOT/design/sys/edk/etc/fast_runtime.opt
   
   In the options for the program map, delete the line "-t 3". The single-core design should then route with no timing violations.
4. Diagnostic test ordering.
   In a hardware regresssion, tests now run without re-downloading the bit file between each tests. This makes it necessary for each test to initialize the core properly. We have noticed that a test named tr_intr2 fails if it is executed after test tr_intr1. Therefore, in our test lists, we have changed the test order so that test tr_intr2 runs first.

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