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The
winners of the OpenSPARC Community Innovation Awards Contest designed
to fuel innovation around chip technology. The contest was part of
Sun's Open Source Community Innovation Awards Program, a multi-year
program running across several open source communities with a $1
Million total prize.
"Sun
developed the Open Source Community Innovation Awards Program to
foster innovation on a global level and recognize the most
interesting initiatives within open source communities worldwide,"
said Shrenik
Mehta, Senior
Director of Frontend Technologies and OpenSPARC program for
Sun Microsystems. "The winners ranged from professors and students
in the academia to developers working in the industry, all of whom
demonstrated extraordinary creativity and collaboration leading to
some outstanding innovations that will have a very real impact on the
OpenSPARC community."
The OpenSPARC Contest Award categories and winners include the following:
- Grand Prize - Martin Johansson, Jiri Gaisler of Gaisler Research
- Best University Level Computer Architecture and/or VLSI course - Mark McDermott, Professor at the University of Texas, Austin
- Best New Bus Interface Creation as a contribution to the OpenSPARC
community - Martin Johansson, Jiri Gaisler of Gaisler Research
- Best Demo of an Application running on an FPGA - Martin Johansson, Jiri Gaisler of Gaisler Research
- Best Adaptation of a Single-thread Application to a Multi-thread
CMT Environment - Andrey Brito, PhD student at the Systems Engineering
Group at the Dresden University of Technology in Germany.
- Best submission that makes a substantial contribution to the
OpenSPARC community and does not constitute any of the other mentioned
categories - Kushal Datta, Graduate student at University of North
Carolina
Listen to the podcast from the winners
The
winners of the OpenSPARC Community Innovation Awards Contest designed
to fuel innovation around chip technology. The contest was part of
Sun's Open Source Community Innovation Awards Program, a multi-year
program running across several open source communities with a $1
Million total prize.
"Sun
developed the Open Source Community Innovation Awards Program to
foster innovation on a global level and recognize the most
interesting initiatives within open source communities worldwide,"
said Shrenik
Mehta, Senior
Director of Frontend Technologies and OpenSPARC program for
Sun Microsystems. "The winners ranged from professors and students
in the academia to developers working in the industry, all of whom
demonstrated extraordinary creativity and collaboration leading to
some outstanding innovations that will have a very real impact on the
OpenSPARC community."
Listen to the podcast from the winners
Best University level Computer Architecture and/or VLSI course, $20,000
Mark McDermott, University of Texas at Austin, Austin, Texas, USA
Mark McDermott is currently an Adjunct Assistant Professor in ECE Department
at the University of Texas where he teaches graduate level courses in
VLSI design, System-on-Chip design and Embedded Systems Architecture.
His current interests include research on methodologies to improve
design and verification productivity in silicon system design. He is a
registered professional engineer and a member of the IEEE, ACM and
TSPE. He has 19 patents and a number of publications in the areas of IC
design and engineering management. He is on the technical advisory
boards of five companies: Obsidian Software Inc., Nascentric, Inc.,
Extreme-DA, Inc., Innovative Silicon, Inc. and Pyxis, Inc.
This course is a graduate level VLSI design course that addresses
one of the shortcomings of most VLSI courses which is the exploration
and design planning that must be performed before the implementation
phase is started. The course teaches the student two basic
capabilities, 1) how to do the early design planning (EDP) of a
microprocessor or SOC using a high level behavioral or RTL model and 2)
how to do the circuit feasibility analysis of the critical speed paths
of the microprocessor or SOC based on the results of the early design
planning. The open source SPARC-T1 was selected for the course project
as it represents a true state of the art microprocessor design. The
design collateral provided by OpenSPARC and SUN is very quality and
provides the students the ability to experience a very realistic design
flow.
Computer Architecture Course (pdf, 4.7MB)
Best New Bus Interface creation as a contribution to the OpenSPARC community, $20,000
Martin Johansson and Jiri Gaisler, Goteborg, Sweden.
Martin Johansson has recently finished his master's degree in computer
science and engineering at Chalmers University. His main research
interests are low-level programming, digital design and computer
security. Prior to his studies, he worked in the telecom industry. In
his spare time, Martin enjoys listening to music and playing guitar.
Jiri Gaisler is the founder and CTO of Gaisler Research, a Swedish
company developing SPARC micro-processors and IP cores. He was previously
a staff researcher at the European Space Agency, where he led the
development of the ERC32 and LEON processors. His research
interests include fault-tolerant processor design and digital
design methodologies.
To be able to use the Sun T1 Niagara processor core with the GRLIB IP
library from Gaisler Research, a PCX/CPX-to-AHB bridge has been
developed. This allows the T1 core to be interfaced to legacy AMBA/AHB
systems, and reuse complex GRLIB cores for ethernet, PCI, USB and DDR.
The bridge support the majority of the PCX packet types, and also
handles cache synchronization in the absence of an L2 cache.
Description (pdf file)
T1 grlib HW (bzip2, 6MB)
Best Demo of an application running on an FPGA, $20,000
Martin Johansson and Jiri Gaisler, Goteborg, Sweden
A T1 Niagara system has been implemented on three different FPGA
boards, using a PCX/CPX-to-AHB bridge and cores from GRLIB. The
systems comprised of a single-thread T1 core, connected to ethernet and
SDRAM interfaces using the AMBA AHB bus. Software applications could be
downloaded via ethernet and executed on the system using the GRMON
debug monitor. The T1 system could operate at 40 MHz in a virtex4
LX60 device, and achieved 20,000 Dhrystones/s (12 DMIPS).
Description (pdf file)
t1 grlib SW (bzip2, 3.2 MB)
Best Adaptation of a single-thread application to a multi-thread CMT (Chip Multi Threaded) environment, $20,000
Andrey Brito, TU Dresden, Germany.
Andrey Brito received his diploma in Electrical Engineering in 2002
from the Federal University of Paraiba, Brazil. In 2004 he received
his diploma in Computer Science and his Master Degree in Informatics
from the Federal University of Campina Grande, Brazil. Since 2006 he
is a PhD student at the Systems Engineering Group at the Dresden
University of Technology, Germany, founded by a DAAD scholarship. His
PhD topic is the engineering of event stream processing systems.
In event stream applications, events flow through a network of
components that perform various types of operations. If the operation
depends only on the current input (i.e., it is stateless),
parallelization can be achieved by simple replication. However, if it
also depends on the component's current state, synchronizing the
access of the different instances to the shared state is often either
inefficient or non-trivial. In this work we use speculation to harness
the power of multi-cores to parallelize stateful components. By
optimistically processing events in parallel and, potentially, out of
order, we reduce processing latency and increase throughput.
Description (.pdf)
workspace_sun_sparc.tgz
workspace_sun_x86.tgz
Best submission that makes a substantial contribution to the
OpenSPARC community and does not constitute any of the above described
Categories, $20,000, $20,000
Kushal Datta, UNC at Charlotte, Charlotte, North Carolina, USA.
Kushal Datta is a doctorate student in University of North Carolina at
Charlotte.
Kushal did his undergraduate from Jadavpur University, Kolkata, India.
His research area include Modelling of Multicore Architectures, Design
Exploration
and Performance Optimization.
CMT Architecture Simulator for Performance, Energy and aRea Analysis
(CASPER), which targets the UltraSPARC T1 multicore CMT architecture,
with each core having multiple hardware strands (multi-threads) or
virtual processing units which can execute in parallel. CASPER is a
multi-threaded (and hence, fast) parameterized cycle-accurate
architecture simulator, which captures the states of (i) the functional
blocks, sub-blocks and register files in all the cores, (ii) shared
memories and (iii) interconnect network, every clock cycle.
Architectural parameters such as number of cores, number of hardware
threads per core (virtual processors), register file size and
organization, branch predictor buffer size and prediction algorithm,
translation lookaside buffer (TLB) size, cache-size and coherence
protocols, memory hierarchy and management, and instruction queue sizes,
to name a few, are parameterized in CASPER. The processor architecture
is a hierarchical design containing functional blocks, such as
Instruction Fetch Unit (IFU), Decode and Branch Unit (DBU), Execution
Unit (EXU) and Load-Store Unit (LSU). These blocks again contain
functional sub-blocks, such as L1 Instruction Cache, Load Miss Queue,
Translation Lookaside Buffer, and so on. The shared memory subsystem can
be configured to consist of either L2 cache or both L2 and L3 unified
caches. The interconnection network is also parameterized. In the first
release, the possible choices are crossbar switch (similar to UltraSPARC
T1), and token-based ring network. http://www.coe.uncc.edu/~kdatta/
CASPER - cycle-accurate simulator of the T1 processor (pdf file)
casper_r1.tar.bz2 (bzip2, 115MB)
Grand Prize Winner, $35,000 Best New Bus Interface creation as a contribution to the OpenSPARC community
Martin Johansson and Jiri Gaisler, Sweden
Thanks for everyone that submitted an entry. We look forward to
more participation and contributions from the community. Thank you to the following people who spent many uncompensated hours reviewing entries. Thank you for helping to make the OpenSPARC
Community Innovation Awards program a success.
- Fred DeSantis, retired technology executive, former Vice President, SPARC
Volume Processors, Sun Microsystem's Microelectronics Group
- Renu Raman, Executive-in-Residence, Tallwood Venture Capital
- Professor Jose Renau, University of California, Santa Cruz, Department
of Computer Engineering
- Paul Hartke, Xilinx University Program, Xilinx Corporation
- Professor Preeti Ranjan Panda, Department of Computer Science &
Engineering, Indian Institute of Technology, New Delhi
- Peggy Aycinena, Editor, EDA Confidential & Contributing Editor EDA Weekly
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