Whats New

The OpenSPARC T2 processor is based on the UltraSPARC T2 processor, the world's fastest commodity processor with eight cores and eight threads per core.

In HW release 1.3, a fully synthesizable, reduced footprint, System-level model has been developed, suitable for FPGA and Emulation Platforms. This model has single OpenSPARC T2 core, crossbar interconnect, and WISHBONE Memory Controller ( from www.opencores.org). This environment supports RTL Simulation, FPGA Synthesis and Gate-level simulation with a one-to-one correspondence (i.e a given test runs unchanged in the RTL & Gate environments.) This environment is hardware platform neutral and can be ported on any FPGA prototyping board.

The software tools portion of the download is at release 1.2.

Read more for new features in HW release 1.3 and SW release 1.2

New Features in the HW Release 1.7 of  OpenSPARC T1

• More Xilinx FPGA support for Virtex 5 FPGAs
• Support for a dual-core system using two OpenSPARC development boards
• Support for Ubuntu Linux boot
• Support for BEE3
• Improved CCX Firmware code
• Improved performance when running regressions of diagnostic tests

For details read more...

The OpenSPARC T2 processor is based on the UltraSPARC T2 processor, the world's fastest commodity processor with eight cores and eight threads per core.

The architecture and performance modeling tools or software portion of the download has been updated to release 1.2. The release contains one major update:

• Added hypervisor/reset support and machine description files for the dual-core OpenSPARC T1 FPGA system. The clock frequency in single core machine description files has been increased.

The chip design and verification or hareware portion of the download is at release 1.2.

Read more for new features in HW release 1.2 and SW release 1.2

EUROPRACTICE Software Service
and
Sun Microsystems, Inc.

Invite you to the

OpenSPARC

Free Introductory Workshop

Brussels, Belgium on April 23rd and 24th

Find out more...

Nangate and Sun Microsystems, Inc. are delighted to announce the interoperability of industry leading open-source 64-bit Chip Multi-threading (CMT) microprocessor design by Sun with Nangate's 45nm Open Cell Library.

Users can now synthesize and optimize state-of-the-art OpenSPARC T1 and OpenSPARC T2 design blocks, using industry standard synthesis tools, on a 45nm technology supplied by Nangate. We believe this combination will facilitate research and experimentation in modern VLSI design topics like timing and noise, reliability, and process variation among other things. We also believe the open-source nature of these two offerings will allow researchers to modify and test new ideas in a consistent and reproducible manner.

Read more...

The OpenSPARC T2 processor is based on the UltraSPARC T2 processor, the world's fastest commodity processor with eight cores and eight threads per core.

Read more for new features in release 1.2

Much more platform support. Machines using the UltraSPARC IV/T1/T2 and Fujitsu SPARC64-V/VI/VII are now supported.

Read the original article: http://openbsd.org/44.html

The winners of the OpenSPARC Community Innovation Awards Contest designed to fuel innovation around chip technology. The contest was part of Sun's Open Source Community Innovation Awards Program, a multi-year program running across several open source communities with a $1 Million total prize.

"Sun developed the Open Source Community Innovation Awards Program to foster innovation on a global level and recognize the most interesting initiatives within open source communities worldwide," said Shrenik Mehta, Senior Director of Frontend Technologies and OpenSPARC program for Sun Microsystems. "The winners ranged from professors and students in the academia to developers working in the industry, all of whom demonstrated extraordinary creativity and collaboration leading to some outstanding innovations that will have a very real impact on the OpenSPARC community."

The OpenSPARC Contest Award categories and winners include the following:

• Grand Prize - Martin Johansson, Jiri Gaisler of Gaisler Research
• Best University Level Computer Architecture and/or VLSI course - Mark McDermott, Professor at the University of Texas, Austin
• Best New Bus Interface Creation as a contribution to the OpenSPARC community - Martin Johansson, Jiri Gaisler of Gaisler Research
• Best Demo of an Application running on an FPGA - Martin Johansson, Jiri Gaisler of Gaisler Research
• Best Adaptation of a Single-thread Application to a Multi-thread CMT Environment - Andrey Brito, PhD student at the Systems Engineering Group at the Dresden University of Technology in Germany.
• Best submission that makes a substantial contribution to the OpenSPARC community and does not constitute any of the other mentioned categories - Kushal Datta, Graduate student at University of North Carolina

At the International Conference for Field Programmable Logic and Applications today, Sun Microsystems, Inc. and Xilinx, Inc. unveiled a feature-rich, high-performance programmable OpenSPARC evaluation platform. The platform provides academic researchers and hardware developers with a flexible OpenSPARC-based platform to create, customize and deploy next-generation applications for a broad set of end markets including supercomputers, industrial, scientific and medical (ISM), aerospace & defense, and storage and networking.

"Our collaboration with industry leaders such as Xilinx will continue to drive the momentum and expansion of the UltraSPARC ecosystem," said Mike Knudsen, vice president, business development and marketing for Sun's Microelectronics unit. "The microprocessor industry is steadily shifting towards CMT architectures, and this new OpenSPARC FPGA evaluation platform puts us in a prime position to enable faster time-to-market for our customers."

Presented at HOTCHIPS20: Rock: A third Generation 65nm, 16-Core, 32 Thread + 32 Scout-Threads CMT SPARC Processor