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ERC Highlights - Dr. James Hoe |
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Friday, 21 March 2008 |
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Excerpts from Education and Research Conference 2008, Dr. James Hoe's highlights from the Panel Discussion at the ERC. (7:27)
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China Universities Join OpenSPARC |
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Friday, 21 March 2008 |
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Sun Microsystems, Inc. and the Ministry of Education
(MOE) for the People's Republic of China announced a three-year
collaboration agreement designed to meet China's demand for cultivating
integrated circuit (IC) engineering talent and industry development. Read more about the announcement and watch video excerpts from Scott McNealy's keynote speech at the Education and
Research Conference 2008 including OpenSPARC and partnership with the
Chinese Ministry of Education. Also Dr. James Hoe's highlights from the
Panel Discussion at the ERC.
Read more... |
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OpenSPARC Workshop in Brazil at University of San Paolo |
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Wednesday, 05 March 2008 |
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University of Sao Paulo (USP), Brazil conducted an OpenSPARC workshop
on March 24-26. Some notes from the first day of the workshop below.
http://www.pad.lsi.usp.br/joomla/index.php?option=com_content&task=view&id=465&Itemid=1
Read
Marcelo Vitor Moretti Arbore blog |
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Tuesday, 05 February 2008 |
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2/5/08: The presentation is a Tutorial on using OpenSPARC T1 in an FPGA, “OpenSPARC T1 FPGA Implementation”
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MICRO-40: Introduction to OpenSPARC |
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Tuesday, 05 February 2008 |
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12/1/07: Tutorial presented at MICRO-40 on December 1-5, 2007, Introduction to OpenSPARC
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Community Innovation Awards Contest |
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Friday, 25 January 2008 |
Want to Win a $20K award? How about an additional Grand Prize Award of $35K? Read on and get your entries in by June 30th!
The OpenSPARC Community Innovation Awards Contest is part of Sun's $1 Million Open Source Community Innovation Awards Program, and will be responsible for awarding $175,000 of the $1 Million total prize. The OpenSPARC Contest awards categories and award amounts are as follows:
OpenSPARC Contest categories and award amounts:
- A. Grand Prize: $35,000
- B. First Prizes: ($20,000 each category)
- i.Best University level Lab Project based on OpenSPARC:
- ii. Best University level Computer Architecture and/or VLSI course
- iii. Best Architecture White paper or Application Notes
- iv. Best New Bus Interface creation as a contribution to the OpenSPARC community
- v. Best Demo of an application running on an FPGA
- vi. Best Adaptation of a single-thread application to a multi-thread CMT (Chip Multi Threaded) environment
- vii. Best submission that makes a substantial contribution to the OpenSPARC community and does not constitute any of the above described Categories
The Grand Prize winner will also be the First Prize Winner in the Category for which the Entry was submitted.
The OpenSPARC Contest will be judged by the OpenSPARC Contest Jury Panel, a group of OpenSPARC industry experts selected from within the OpenSPARC community representing a diverse background of expertise and experience.
Read the complete contest rules.
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OpenSPARC Course Material |
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Monday, 10 December 2007 |
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Collaborate and share course material related to OpenSPARC,
chip multi-threading, multi-core in many areas including hardware design,
design tools, CMT Architecture, software systems design, operating systems,
concurrent computing and other related areas. We're looking for
professors who have a passion for teaching and contributing
to their field of study by sharing their course material with others.
Take a look at site we are developing and the course materials already available:
http://wiki.opensparc.net/bin/view.pl/CourseMaterial.
We thankful for the support
and generosity of professors who choose to share their
research, pedagogy, and knowledge to benefit
others. |
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OpenSPARC Centers of Excellence |
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Friday, 07 December 2007 |
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Seven major universities are now official OpenSPARC
Technology Centers of Excellence:
- University of California, Santa
Cruz
- University of Texas, Austin
- University of Michigan, Ann Arbor
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University of Illinois, Urbana-Champaign
- Carnegie Mellon
University
- Stanford University
- University of Otago, Dunedin, New Zealand
Each Center of Excellence has a minimum two-year
commitment, during which time they'll execute chip design research
and course work based on Sun's chip multi-threading (CMT) design.
Visit our Centers
of Excellence web page. |
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Paper presented at A-SSCC 2007 |
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Friday, 07 December 2007 |
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12/6/07: Paper presented at A-SSCC 2007 on November 12-14, 2007, UltraSPARC T2: A Highly-Threaded, Power-Efficient, SPARC SOC |
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Several Updated and New Sun Blueprints |
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Friday, 07 December 2007 |
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12/7/07: Several Updated and New Sun Blueprints
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Updated OpenSPARC T2 Specs |
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Presentation and Paper from HLDVT 07 |
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Wednesday, 14 November 2007 |
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11/14/07 - A paper and presentation from HLDVT 07, High Level Design Validation and Test Workshop 2007, on November 7-8, 2007 at Irvine, CA.
Paper: “Coverage-directed test generation through automatic constraint extraction“
by Onur Guzey and Li-C. Wang, University of California Santa Barbara
Presentation: “Post-Silicon Verification Methodology on Sun's UltraSPARC T2 Processor“
by Jai Kumar, Verification Technologist, Catherine Ahlschlager, Manager, Formal Verification
and Peter Isberg, Manager, Test Generation Technologies, Sun Microsystems
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OpenSPARC T2 Beta Program Closing |
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Tuesday, 13 November 2007 |
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11/13/07 - Last chance to apply for the OpenSPARC T2 beta program, we're closing
the beta program this Friday Nov. 16, 2007.
FAQ:
http://www.opensparc.net/faqs/opensparc-t2/
OpenSPARC T2 Specifications released:
http://www.opensparc.net/opensparc-t2/index.html
Next opportunity to look at the OpenSPARC T2 RTL code will be when its released. (which will not be too long from now)
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Electric Floorplan of OpenSPARC T1 |
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Monday, 29 October 2007 |
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10/29/07 - The Electric VLSI Design System is an open-source Electronic Design
Automation (EDA) system that can handle many forms of circuit design,
including custom IC layout, Schematic Capture (digital and analog),
textual languages such as VHDL/Verilog, and much more. It has many
built-in tools (DRC, ERC, simulators, generators, routers, etc.) and
built-in technologies (different CMOS variations, nMos, Bipolar,
etc.) The software is available at www.staticfreesoft.com
The OpenSPARC team has done some initial work with using Electric to generate a floorplan using Electric.
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Thursday, 30 August 2007 |
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8/30/07: Updated Fan Buttons. |
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Updated OpenSPARC T1 Microarchitecture Specification |
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Tuesday, 28 August 2007 |
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8/27/07: Updated OpenSPARC T1 Micro Architecture Specification to reflect changes with release 1.5 |
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HOTCHIPS19: VictoriaFalls: Scaling Highly-Threaded Processor Cores |
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Thursday, 23 August 2007 |
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8/21/07: Presentation made at the HOT CHIPS 19, on August 20-21, 2007, Stanford, CA.
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Wednesday, 22 August 2007 |
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The Transplant project provides the capability for simulating
portions of real-world, full-system workloads on the OpenSPARC
RTL. The key idea is to "transplant" architectural register and
memory state from full-system functional simulators such as SAM
and Simics to the RTL model. This process allows RTL simulation
for workloads such as operating systems and databases that are
otherwise too slow to simulate or require resources (e.g., I/O)
that are not modeled in RTL.
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OpenSPARC T1 Version 1.6 Released |
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Tuesday, 14 August 2007 |
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New Features in the Release 1.6 of OpenSPARC T1
- T1 core supports single- and four-thread options on FPGAs
- Reference designs boot OpenSolaris on single- or four-thread mode
- Xilinx Virtex-5 technology support
- Networking (ftp, telnet) support
These new features are designed to enable a user to build real systems using the OpenSPARC T1 core.
For further details on Xilinx, please refer to the Xilinx University program.
Download Details
and OpenSPARC T1 Specfications |
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Updated Sun Blueprint, Beginners Guide to LDoms: Understanding and Deploying Logical Domains |
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