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S
 sb_crc_error_injector
File:sb_crc_error_injector.v
 sb_decode_crc
File:sb_decode_crc.v
Instantiates:voting_logic:check_LSB3 , beh_fifo:buffer_fifo0 , beh_fifo:buffer_fifo1 , beh_fifo:write_fifo , beh_fifo:read_fifo , dff_n:WF0 , dff_n:WF1 , dff_n:WF2 , dff_fbd:WCR1 , dff_fbd:WCR2 , dff_fbd:WCR3 , dff_fbd:WCR4 , dff_fbd:sync1 , dff_fbd:sync2 , dff_fbd:sync3 , dff_fbd:sync4 , dff_fbd:sync5 , dff_fbd:sync6 , dff_fbd:sync7 , crc_FE:data_crc , crc_aE:cmd_crc , crc_FE_failover:data_crc_failover , crc_aE_failover:cmd_crc_failover 
Instantiated by:amb_top:sb_decoder 
 send_ts0
File:send_ts0.v
 serdes_wrapper
File:serdes_wrapper.v
Instantiates:clock_multiplier_10x:clock_multiplier_10x , xaui:xaui0 
Instantiated by:enet_models:serdes_P0 , enet_models:serdes_P1 
 shifter
File:delay.v
Instantiates:dff_n:dff0 , dff_n:dff1 , dff_n:dff2 , dff_n:dff3 , dff_n:dff4 , dff_n:dff5 , dff_n:dff6 , dff_n:dff7 , dff_n:dff8 , dff_n:dff9 , dff_n:dff10 , dff_n:dff11 , dff_n:dff12 , dff_n:dff13 , dff_n:dff14 , dff_n:dff15 , dff_n:dff16 , dff_n:dff17 , dff_n:dff18 , dff_n:dff19 , dff_n:dff20 , dff_n:dff21 , dff_n:dff22 , dff_n:dff23 , dff_n:dff24 , dff_n:dff25 , dff_n:dff26 , dff_n:dff27 , dff_n:dff28 , dff_n:dff29 , dff_n:dff30 , dff_n:dff31 , dff_n:dff32 , dff_n:dff33 , dff_n:dff34 , dff_n:dff35 , dff_n:dff36 , dff_n:dff37 , dff_n:dff38 , dff_n:dff39 , dff_n:dff40 , dff_n:dff41 , dff_n:dff42 , dff_n:dff43 , dff_n:dff44 , dff_n:dff45 , dff_n:dff46 , dff_n:dff47 , dff_n:dff48 , dff_n:dff49 , dff_n:dff50 , dff_n:dff51 , dff_n:dff52 , dff_n:dff53 , dff_n:dff54 , dff_n:dff55 , dff_n:dff56 , dff_n:dff57 , dff_n:dff58 , dff_n:dff59 , dff_n:dff60 , dff_n:dff61 , dff_n:dff62 , dff_n:dff63 , dff_n:dff64 , dff_n:dff65 , dff_n:dff66 , dff_n:dff67 , dff_n:dff68 , dff_n:dff69 , dff_n:dff70 , dff_n:dff71 , dff_n:dff72 , dff_n:dff73 , dff_n:dff74 , dff_n:dff75 , dff_n:dff76 , dff_n:dff77 , dff_n:dff78 , dff_n:dff79 , dff_n:dff80 , dff_n:dff81 , dff_n:dff82 , dff_n:dff83 , dff_n:dff84 , dff_n:dff85 , dff_n:dff86 , dff_n:dff87 , dff_n:dff88 , dff_n:dff89 , dff_n:dff90 , dff_n:dff91 , dff_n:dff92 , dff_n:dff93 , dff_n:dff94 , dff_n:dff95 , dff_n:dff96 , dff_n:dff97 , dff_n:dff98 , dff_n:dff99 , dff_n:dff100 , dff_n:dff101 , dff_n:dff102 , dff_n:dff103 , dff_n:dff104 , dff_n:dff105 , dff_n:dff106 , dff_n:dff107 , dff_n:dff108 , dff_n:dff109 , dff_n:dff110 , dff_n:dff111 , dff_n:dff112 , dff_n:dff113 , dff_n:dff114 , dff_n:dff115 , dff_n:dff116 , dff_n:dff117 , dff_n:dff118 , dff_n:dff119 , dff_n:dff120 , dff_n:dff121 , dff_n:dff122 , dff_n:dff123 , dff_n:dff124 , dff_n:dff125 , dff_n:dff126 , dff_n:dff127 , dff_n:dff128 , dff_n:dff129 , dff_n:dff130 , dff_n:dff131 , dff_n:dff132 , dff_n:dff133 , dff_n:dff134 , dff_n:dff135 , dff_n:dff136 , dff_n:dff137 , dff_n:dff138 , dff_n:dff139 , dff_n:dff140 , dff_n:dff141 , dff_n:dff142 , dff_n:dff143 , dff_n:dff144 , dff_n:dff145 , dff_n:dff146 , dff_n:dff147 , dff_n:dff148 , dff_n:dff149 , dff_n:dff150 , dff_n:dff151 , dff_n:dff152 , dff_n:dff153 , dff_n:dff154 , dff_n:dff155 , dff_n:dff156 , dff_n:dff157 , dff_n:dff158 , dff_n:dff159 , dff_n:dff160 , dff_n:dff161 , dff_n:dff162 , dff_n:dff163 , dff_n:dff164 , dff_n:dff165 , dff_n:dff166 , dff_n:dff167 
Instantiated by:nb_encode_crc:config_rd_ctrl_shft_data , nb_encode_crc:sync_data_shift 
 shifter_p
File:delay.v
Instantiates:dff_p:dff0 , dff_p:dff1 , dff_p:dff2 , dff_p:dff3 , dff_p:dff4 , dff_p:dff5 , dff_p:dff6 , dff_p:dff7 , dff_p:dff8 , dff_p:dff9 , dff_p:dff10 , dff_p:dff11 , dff_p:dff12 , dff_p:dff13 , dff_p:dff14 , dff_p:dff15 , dff_p:dff16 , dff_p:dff17 , dff_p:dff18 , dff_p:dff19 , dff_p:dff20 , dff_p:dff21 , dff_p:dff22 , dff_p:dff23 , dff_p:dff24 , dff_p:dff25 , dff_p:dff26 , dff_p:dff27 , dff_p:dff28 , dff_p:dff29 , dff_p:dff30 , dff_p:dff31 , dff_p:dff32 , dff_p:dff33 , dff_p:dff34 , dff_p:dff35 , dff_p:dff36 , dff_p:dff37 , dff_p:dff38 , dff_p:dff39 , dff_p:dff40 , dff_p:dff41 , dff_p:dff42 , dff_p:dff43 , dff_p:dff44 , dff_p:dff45 , dff_p:dff46 , dff_p:dff47 , dff_p:dff48 , dff_p:dff49 , dff_p:dff50 , dff_p:dff51 , dff_p:dff52 , dff_p:dff53 , dff_p:dff54 , dff_p:dff55 , dff_p:dff56 , dff_p:dff57 , dff_p:dff58 , dff_p:dff59 , dff_p:dff60 , dff_p:dff61 , dff_p:dff62 , dff_p:dff63 , dff_p:dff64 , dff_p:dff65 , dff_p:dff66 , dff_p:dff67 , dff_p:dff68 , dff_p:dff69 , dff_p:dff70 , dff_p:dff71 , dff_p:dff72 , dff_p:dff73 , dff_p:dff74 , dff_p:dff75 , dff_p:dff76 , dff_p:dff77 , dff_p:dff78 , dff_p:dff79 , dff_p:dff80 , dff_p:dff81 , dff_p:dff82 , dff_p:dff83 , dff_p:dff84 , dff_p:dff85 , dff_p:dff86 , dff_p:dff87 , dff_p:dff88 , dff_p:dff89 , dff_p:dff90 , dff_p:dff91 , dff_p:dff92 , dff_p:dff93 , dff_p:dff94 , dff_p:dff95 , dff_p:dff96 , dff_p:dff97 , dff_p:dff98 , dff_p:dff99 , dff_p:dff100 , dff_p:dff101 , dff_p:dff102 , dff_p:dff103 , dff_p:dff104 , dff_p:dff105 , dff_p:dff106 , dff_p:dff107 , dff_p:dff108 , dff_p:dff109 , dff_p:dff110 , dff_p:dff111 , dff_p:dff112 , dff_p:dff113 , dff_p:dff114 , dff_p:dff115 , dff_p:dff116 , dff_p:dff117 , dff_p:dff118 , dff_p:dff119 , dff_p:dff120 , dff_p:dff121 , dff_p:dff122 , dff_p:dff123 , dff_p:dff124 , dff_p:dff125 , dff_p:dff126 , dff_p:dff127 , dff_p:dff128 , dff_p:dff129 , dff_p:dff130 , dff_p:dff131 , dff_p:dff132 , dff_p:dff133 , dff_p:dff134 , dff_p:dff135 , dff_p:dff136 , dff_p:dff137 , dff_p:dff138 , dff_p:dff139 , dff_p:dff140 , dff_p:dff141 , dff_p:dff142 , dff_p:dff143 , dff_p:dff144 , dff_p:dff145 , dff_p:dff146 , dff_p:dff147 , dff_p:dff148 , dff_p:dff149 , dff_p:dff150 , dff_p:dff151 , dff_p:dff152 , dff_p:dff153 , dff_p:dff154 , dff_p:dff155 , dff_p:dff156 , dff_p:dff157 , dff_p:dff158 , dff_p:dff159 , dff_p:dff160 , dff_p:dff161 , dff_p:dff162 , dff_p:dff163 , dff_p:dff164 , dff_p:dff165 , dff_p:dff166 , dff_p:dff167 , dff_p:dff168 , dff_p:dff169 , dff_p:dff170 , dff_p:dff171 , dff_p:dff172 , dff_p:dff173 , dff_p:dff174 , dff_p:dff175 , dff_p:dff176 , dff_p:dff177 , dff_p:dff178 , dff_p:dff179 , dff_p:dff180 , dff_p:dff181 , dff_p:dff182 , dff_p:dff183 , dff_p:dff184 , dff_p:dff185 , dff_p:dff186 , dff_p:dff187 , dff_p:dff188 , dff_p:dff189 , dff_p:dff190 , dff_p:dff191 , dff_p:dff192 , dff_p:dff193 , dff_p:dff194 , dff_p:dff195 , dff_p:dff196 , dff_p:dff197 , dff_p:dff198 , dff_p:dff199 , dff_p:dff200 
Instantiated by:dtm_training:delay_tr_complete1 , dtm_training:delay_tr_complete2 , channel_mon:alert_frm_dly , channel_mon:read_cmd_delay_d1 , channel_mon:read_cmd_delay_d2 , channel_mon:read_cmd_delay_d3 , channel_mon:sync_cmd_delay_d1 , channel_mon:sync_cmd_delay_d2 , training_sequence_fsm:train_delay , amb_init:shft0 , amb_init:shft1 , amb_init:shft2 , amb_init:shft3 , amb_init:shft4 , amb_init:shft5 , amb_init:shft6 , amb_init:shft7 , amb_init:shft8 , amb_init:shft9 , amb_init:shft10 , amb_init:shft11 
 shifter_UI_p
File:delay.v
Instantiates:dff_p:dff0 , dff_p:dff1 , dff_p:dff2 , dff_p:dff3 , dff_p:dff4 , dff_p:dff5 , dff_p:dff6 , dff_p:dff7 , dff_p:dff8 , dff_p:dff9 , dff_p:dff10 , dff_p:dff11 , dff_p:dff12 , dff_p:dff13 , dff_p:dff14 , dff_p:dff15 , dff_p:dff16 , dff_p:dff17 , dff_p:dff18 , dff_p:dff19 , dff_p:dff20 , dff_p:dff21 , dff_p:dff22 , dff_p:dff23 , dff_p:dff24 , dff_p:dff25 , dff_p:dff26 , dff_p:dff27 , dff_p:dff28 , dff_p:dff29 , dff_p:dff30 , dff_p:dff31 , dff_p:dff32 , dff_p:dff33 , dff_p:dff34 , dff_p:dff35 , dff_p:dff36 , dff_p:dff37 , dff_p:dff38 , dff_p:dff39 , dff_p:dff40 , dff_p:dff41 , dff_p:dff42 , dff_p:dff43 , dff_p:dff44 , dff_p:dff45 , dff_p:dff46 , dff_p:dff47 , dff_p:dff48 , dff_p:dff49 , dff_p:dff50 , dff_p:dff51 , dff_p:dff52 , dff_p:dff53 , dff_p:dff54 , dff_p:dff55 , dff_p:dff56 , dff_p:dff57 , dff_p:dff58 , dff_p:dff59 , dff_p:dff60 , dff_p:dff61 , dff_p:dff62 , dff_p:dff63 , dff_p:dff64 , dff_p:dff65 , dff_p:dff66 , dff_p:dff67 , dff_p:dff68 , dff_p:dff69 , dff_p:dff70 , dff_p:dff71 , dff_p:dff72 , dff_p:dff73 , dff_p:dff74 , dff_p:dff75 , dff_p:dff76 , dff_p:dff77 , dff_p:dff78 , dff_p:dff79 , dff_p:dff80 , dff_p:dff81 , dff_p:dff82 , dff_p:dff83 , dff_p:dff84 , dff_p:dff85 , dff_p:dff86 , dff_p:dff87 , dff_p:dff88 , dff_p:dff89 , dff_p:dff90 , dff_p:dff91 , dff_p:dff92 , dff_p:dff93 , dff_p:dff94 , dff_p:dff95 , dff_p:dff96 , dff_p:dff97 , dff_p:dff98 , dff_p:dff99 , dff_p:dff100 , dff_p:dff101 , dff_p:dff102 , dff_p:dff103 , dff_p:dff104 , dff_p:dff105 , dff_p:dff106 , dff_p:dff107 , dff_p:dff108 , dff_p:dff109 , dff_p:dff110 , dff_p:dff111 , dff_p:dff112 , dff_p:dff113 , dff_p:dff114 , dff_p:dff115 , dff_p:dff116 , dff_p:dff117 , dff_p:dff118 , dff_p:dff119 , dff_p:dff120 , dff_p:dff121 , dff_p:dff122 , dff_p:dff123 , dff_p:dff124 , dff_p:dff125 , dff_p:dff126 , dff_p:dff127 , dff_p:dff128 , dff_p:dff129 , dff_p:dff130 , dff_p:dff131 , dff_p:dff132 , dff_p:dff133 , dff_p:dff134 , dff_p:dff135 , dff_p:dff136 , dff_p:dff137 , dff_p:dff138 , dff_p:dff139 , dff_p:dff140 , dff_p:dff141 , dff_p:dff142 , dff_p:dff143 , dff_p:dff144 , dff_p:dff145 , dff_p:dff146 , dff_p:dff147 , dff_p:dff148 , dff_p:dff149 , dff_p:dff150 , dff_p:dff151 , dff_p:dff152 , dff_p:dff153 , dff_p:dff154 , dff_p:dff155 , dff_p:dff156 , dff_p:dff157 , dff_p:dff158 , dff_p:dff159 , dff_p:dff160 , dff_p:dff161 , dff_p:dff162 , dff_p:dff163 , dff_p:dff164 , dff_p:dff165 , dff_p:dff166 , dff_p:dff167 , dff_p:dff168 , dff_p:dff169 , dff_p:dff170 , dff_p:dff171 , dff_p:dff172 , dff_p:dff173 , dff_p:dff174 , dff_p:dff175 , dff_p:dff176 , dff_p:dff177 , dff_p:dff178 , dff_p:dff179 , dff_p:dff180 , dff_p:dff181 , dff_p:dff182 , dff_p:dff183 , dff_p:dff184 , dff_p:dff185 , dff_p:dff186 , dff_p:dff187 , dff_p:dff188 , dff_p:dff189 , dff_p:dff190 , dff_p:dff191 , dff_p:dff192 , dff_p:dff193 , dff_p:dff194 , dff_p:dff195 , dff_p:dff196 , dff_p:dff197 , dff_p:dff198 , dff_p:dff199 , dff_p:dff200 
Instantiated by:nb_encode_crc:config_rd_ctrl_shft , nb_encode_crc:shft , nb_encode_crc:sync_ctrl_shift 
 sii
File:sii.v
Instantiates:n2_com_dp_32x82_cust:ildq0 , sii_ild_dp:ild0 , sii_ilc_ctl:ilc0 , n2_com_dp_32x82_cust:ildq1 , sii_ild_dp:ild1 , sii_ilc_ctl:ilc1 , n2_com_dp_32x82_cust:ildq2 , sii_ild_dp:ild2 , sii_ilc_ctl:ilc2 , n2_com_dp_32x82_cust:ildq3 , sii_ild_dp:ild3 , sii_ilc_ctl:ilc3 , n2_com_dp_32x82_cust:ildq4 , sii_ild_dp:ild4 , sii_ilc_ctl:ilc4 , n2_com_dp_32x82_cust:ildq5 , sii_ild_dp:ild5 , sii_ilc_ctl:ilc5 , n2_com_dp_32x82_cust:ildq6 , sii_ild_dp:ild6 , sii_ilc_ctl:ilc6 , n2_com_dp_32x82_cust:ildq7 , sii_ild_dp:ild7 , sii_ilc_ctl:ilc7 , n2_com_dp_64x72_cust:indq , sii_inc_ctl:inc , sii_ipcc_ctl:ipcc , sii_ipcs_ctl:ipcs0 , sii_ipcs_ctl:ipcs1 , n2_com_dp_64x80_cust:ipdodq0_h , n2_com_dp_64x80_cust:ipdodq0_l , n2_com_dp_64x80_cust:ipdbdq0_h , n2_com_dp_64x80_cust:ipdbdq0_l , n2_com_dp_16x72_cust:ipdohq0 , n2_com_dp_16x72_cust:ipdbhq0 , sii_ipcc_dp:ipcc_dp , sii_mb0_ctl:mb0 , sii_mb1_ctl:mb1 , clkgen_sii_cmp:clkgen_cmp , clkgen_sii_io:clkgen_io , sii_stgsio_dp:stgsio_dp , n2_com_dp_64x80_cust:ipdodq1_h , n2_com_dp_64x80_cust:ipdodq1_l , n2_com_dp_64x80_cust:ipdbdq1_h , n2_com_dp_64x80_cust:ipdbdq1_l , n2_com_dp_16x72_cust:ipdohq1 , n2_com_dp_16x72_cust:ipdbhq1 
Instantiated by:cpu:sii 
 sii_ilc_ctl
File:sii_ilc_ctl.v
Instantiates:sii_ilc_ctll1clkhdr_ctl_macro:clkgen , sii_ilc_ctlspare_ctl_macro__num_6:spares , sii_ilc_ctlmsff_ctl_macro__width_5:reg_curhdr_58_56 , sii_ilc_ctlmsff_ctl_macro__width_5:reg_pre_curhdr0 , sii_ilc_ctlmsff_ctl_macro__width_5:reg_pre_curhdr1 , sii_ilc_ctlmsff_ctl_macro__width_5:reg_pre_curhdr2 , sii_ilc_ctlmsff_ctl_macro__width_5:reg_pre_curhdr3 , sii_ilc_ctlmsff_ctl_macro__width_1:reg_sii_l2t_req_vld , sii_ilc_ctlmsff_ctl_macro__width_2:reg_sii_dbg_l2t_req , sii_ilc_ctlmsff_ctl_macro__width_6:reg_cstate , sii_ilc_ctlmsff_ctl_macro__width_3:reg_sio_cnt , sii_ilc_ctlmsff_ctl_macro__width_4:reg_wri_cnt , sii_ilc_ctlmsff_ctl_macro__width_3:reg_wrm_cnt , sii_ilc_ctlmsff_ctl_macro__width_2:reg_l2iq_cnt_r , sii_ilc_ctlmsff_ctl_macro__width_3:reg_l2wib_cnt_r , sii_ilc_ctlmsff_ctl_macro__width_3:reg_hdr_rd_ptr , sii_ilc_ctlmsff_ctl_macro__width_3:reg_hdr_wr_ptr , sii_ilc_ctlmsff_ctl_macro__width_6:reg_ilc_ildq_rd_addr , sii_ilc_ctlmsff_ctl_macro__width_1:reg_ilc_ildq_rd_en , sii_ilc_ctlmsff_ctl_macro__width_1:reg_wrm_end , sii_ilc_ctlmsff_ctl_macro__width_3:reg_cmd , sii_ilc_ctlmsff_ctl_macro__width_1:reg_dmu_wrm , sii_ilc_ctlmsff_ctl_macro__width_1:reg_niu_wrm , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be00 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be01 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be02 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be03 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be04 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be05 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be06 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be07 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be10 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be11 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be12 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be13 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be14 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be15 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be16 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be17 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be20 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be21 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be22 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be23 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be24 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be25 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be26 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be27 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be30 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be31 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be32 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be33 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be34 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be35 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be36 , sii_ilc_ctlmsff_ctl_macro__en_1__width_8:reg_be37 , sii_ilc_ctlmsff_ctl_macro__width_1:reg_sii_mb0_run , sii_ilc_ctlmsff_ctl_macro__width_1:reg_sii_mb0_rd_en , sii_ilc_ctlmsff_ctl_macro__width_5:reg_sii_mb0_addr , sii_ilc_ctlmsff_ctl_macro__width_4:reg_ilc_ild_addr_h , sii_ilc_ctlmsff_ctl_macro__width_4:reg_ilc_ild_addr_lo 
Instantiated by:sii:ilc0 , sii:ilc1 , sii:ilc2 , sii:ilc3 , sii:ilc4 , sii:ilc5 , sii:ilc6 , sii:ilc7 
 sii_ilc_ctll1clkhdr_ctl_macro
File:sii_ilc_ctl.v
Instantiates:cl_sc1_l1hdr_8x:c_0 
Instantiated by:sii_ilc_ctl:clkgen 
 sii_ilc_ctlmsff_ctl_macro__en_1__width_8
File:sii_ilc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ilc_ctl:reg_be00 , sii_ilc_ctl:reg_be01 , sii_ilc_ctl:reg_be02 , sii_ilc_ctl:reg_be03 , sii_ilc_ctl:reg_be04 , sii_ilc_ctl:reg_be05 , sii_ilc_ctl:reg_be06 , sii_ilc_ctl:reg_be07 , sii_ilc_ctl:reg_be10 , sii_ilc_ctl:reg_be11 , sii_ilc_ctl:reg_be12 , sii_ilc_ctl:reg_be13 , sii_ilc_ctl:reg_be14 , sii_ilc_ctl:reg_be15 , sii_ilc_ctl:reg_be16 , sii_ilc_ctl:reg_be17 , sii_ilc_ctl:reg_be20 , sii_ilc_ctl:reg_be21 , sii_ilc_ctl:reg_be22 , sii_ilc_ctl:reg_be23 , sii_ilc_ctl:reg_be24 , sii_ilc_ctl:reg_be25 , sii_ilc_ctl:reg_be26 , sii_ilc_ctl:reg_be27 , sii_ilc_ctl:reg_be30 , sii_ilc_ctl:reg_be31 , sii_ilc_ctl:reg_be32 , sii_ilc_ctl:reg_be33 , sii_ilc_ctl:reg_be34 , sii_ilc_ctl:reg_be35 , sii_ilc_ctl:reg_be36 , sii_ilc_ctl:reg_be37 
 sii_ilc_ctlmsff_ctl_macro__width_1
File:sii_ilc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ilc_ctl:reg_sii_l2t_req_vld , sii_ilc_ctl:reg_ilc_ildq_rd_en , sii_ilc_ctl:reg_wrm_end , sii_ilc_ctl:reg_dmu_wrm , sii_ilc_ctl:reg_niu_wrm , sii_ilc_ctl:reg_sii_mb0_run , sii_ilc_ctl:reg_sii_mb0_rd_en 
 sii_ilc_ctlmsff_ctl_macro__width_2
File:sii_ilc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ilc_ctl:reg_sii_dbg_l2t_req , sii_ilc_ctl:reg_l2iq_cnt_r 
 sii_ilc_ctlmsff_ctl_macro__width_3
File:sii_ilc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ilc_ctl:reg_sio_cnt , sii_ilc_ctl:reg_wrm_cnt , sii_ilc_ctl:reg_l2wib_cnt_r , sii_ilc_ctl:reg_hdr_rd_ptr , sii_ilc_ctl:reg_hdr_wr_ptr , sii_ilc_ctl:reg_cmd 
 sii_ilc_ctlmsff_ctl_macro__width_4
File:sii_ilc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ilc_ctl:reg_wri_cnt , sii_ilc_ctl:reg_ilc_ild_addr_h , sii_ilc_ctl:reg_ilc_ild_addr_lo 
 sii_ilc_ctlmsff_ctl_macro__width_5
File:sii_ilc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ilc_ctl:reg_curhdr_58_56 , sii_ilc_ctl:reg_pre_curhdr0 , sii_ilc_ctl:reg_pre_curhdr1 , sii_ilc_ctl:reg_pre_curhdr2 , sii_ilc_ctl:reg_pre_curhdr3 , sii_ilc_ctl:reg_sii_mb0_addr 
 sii_ilc_ctlmsff_ctl_macro__width_6
File:sii_ilc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ilc_ctl:reg_cstate , sii_ilc_ctl:reg_ilc_ildq_rd_addr 
 sii_ilc_ctlspare_ctl_macro__num_6
File:sii_ilc_ctl.v
Instantiates:cl_sc1_msff_8x:spare0_flop , cl_u1_buf_32x:spare0_buf_32x , cl_u1_nand3_8x:spare0_nand3_8x , cl_u1_inv_8x:spare0_inv_8x , cl_u1_aoi22_4x:spare0_aoi22_4x , cl_u1_buf_8x:spare0_buf_8x , cl_u1_oai22_4x:spare0_oai22_4x , cl_u1_inv_16x:spare0_inv_16x , cl_u1_nand2_16x:spare0_nand2_16x , cl_u1_nor3_4x:spare0_nor3_4x , cl_u1_nand2_8x:spare0_nand2_8x , cl_u1_buf_16x:spare0_buf_16x , cl_u1_nor2_16x:spare0_nor2_16x , cl_u1_inv_32x:spare0_inv_32x , cl_sc1_msff_8x:spare1_flop , cl_u1_buf_32x:spare1_buf_32x , cl_u1_nand3_8x:spare1_nand3_8x , cl_u1_inv_8x:spare1_inv_8x , cl_u1_aoi22_4x:spare1_aoi22_4x , cl_u1_buf_8x:spare1_buf_8x , cl_u1_oai22_4x:spare1_oai22_4x , cl_u1_inv_16x:spare1_inv_16x , cl_u1_nand2_16x:spare1_nand2_16x , cl_u1_nor3_4x:spare1_nor3_4x , cl_u1_nand2_8x:spare1_nand2_8x , cl_u1_buf_16x:spare1_buf_16x , cl_u1_nor2_16x:spare1_nor2_16x , cl_u1_inv_32x:spare1_inv_32x , cl_sc1_msff_8x:spare2_flop , cl_u1_buf_32x:spare2_buf_32x , cl_u1_nand3_8x:spare2_nand3_8x , cl_u1_inv_8x:spare2_inv_8x , cl_u1_aoi22_4x:spare2_aoi22_4x , cl_u1_buf_8x:spare2_buf_8x , cl_u1_oai22_4x:spare2_oai22_4x , cl_u1_inv_16x:spare2_inv_16x , cl_u1_nand2_16x:spare2_nand2_16x , cl_u1_nor3_4x:spare2_nor3_4x , cl_u1_nand2_8x:spare2_nand2_8x , cl_u1_buf_16x:spare2_buf_16x , cl_u1_nor2_16x:spare2_nor2_16x , cl_u1_inv_32x:spare2_inv_32x , cl_sc1_msff_8x:spare3_flop , cl_u1_buf_32x:spare3_buf_32x , cl_u1_nand3_8x:spare3_nand3_8x , cl_u1_inv_8x:spare3_inv_8x , cl_u1_aoi22_4x:spare3_aoi22_4x , cl_u1_buf_8x:spare3_buf_8x , cl_u1_oai22_4x:spare3_oai22_4x , cl_u1_inv_16x:spare3_inv_16x , cl_u1_nand2_16x:spare3_nand2_16x , cl_u1_nor3_4x:spare3_nor3_4x , cl_u1_nand2_8x:spare3_nand2_8x , cl_u1_buf_16x:spare3_buf_16x , cl_u1_nor2_16x:spare3_nor2_16x , cl_u1_inv_32x:spare3_inv_32x , cl_sc1_msff_8x:spare4_flop , cl_u1_buf_32x:spare4_buf_32x , cl_u1_nand3_8x:spare4_nand3_8x , cl_u1_inv_8x:spare4_inv_8x , cl_u1_aoi22_4x:spare4_aoi22_4x , cl_u1_buf_8x:spare4_buf_8x , cl_u1_oai22_4x:spare4_oai22_4x , cl_u1_inv_16x:spare4_inv_16x , cl_u1_nand2_16x:spare4_nand2_16x , cl_u1_nor3_4x:spare4_nor3_4x , cl_u1_nand2_8x:spare4_nand2_8x , cl_u1_buf_16x:spare4_buf_16x , cl_u1_nor2_16x:spare4_nor2_16x , cl_u1_inv_32x:spare4_inv_32x , cl_sc1_msff_8x:spare5_flop , cl_u1_buf_32x:spare5_buf_32x , cl_u1_nand3_8x:spare5_nand3_8x , cl_u1_inv_8x:spare5_inv_8x , cl_u1_aoi22_4x:spare5_aoi22_4x , cl_u1_buf_8x:spare5_buf_8x , cl_u1_oai22_4x:spare5_oai22_4x , cl_u1_inv_16x:spare5_inv_16x , cl_u1_nand2_16x:spare5_nand2_16x , cl_u1_nor3_4x:spare5_nor3_4x , cl_u1_nand2_8x:spare5_nand2_8x , cl_u1_buf_16x:spare5_buf_16x , cl_u1_nor2_16x:spare5_nor2_16x , cl_u1_inv_32x:spare5_inv_32x 
Instantiated by:sii_ilc_ctl:spares 
 sii_ild_dp
File:sii_ild_dp.v
Instantiates:sii_ild_dpinv_macro__width_2:inv_fail , sii_ild_dpmsff_macro__stack_2c__width_2:ff_sii_mb0_ild_fail , sii_ild_dpmsff_macro__stack_8c__width_8:ff_sii_mb0_wdata_rrr , sii_ild_dpmsff_macro__stack_8c__width_8:ff_sii_mb0_wdata_rr , sii_ild_dpmsff_macro__stack_8c__width_8:ff_sii_mb0_wdata_r , sii_ild_dpcmp_macro__dcmp_8x__width_32:cmp_81_64 , sii_ild_dpcmp_macro__dcmp_8x__width_64:cmp_63_0 , sii_ild_dpmsff_macro__stack_8c__width_8:ff_sii_l2b_ecc , sii_ild_dpmux_macro__mux_aonpe__ports_2__stack_32r__width_8:mux_sii_l2b_ecc_hdr , sii_ild_dpmux_macro__mux_aonpe__ports_2__stack_32r__width_8:mux_sii_l2b_ecc , sii_ild_dpmsff_macro__dmsff_32x__stack_32c__width_32:ff_sii_l2t_req , sii_ild_dpmux_macro__dmux_8x__mux_aonpe__ports_4__stack_32l__width_32:mux_sii_l2t_req , sii_ild_dpand_macro__left_0__ports_2__stack_4r__width_2:and_data_cyc_sel , sii_ild_dpmux_macro__dmux_8x__mux_aonpe__ports_4__stack_36r__width_36:mux_ild_ilc_curhdr_h , sii_ild_dpmux_macro__dmux_8x__mux_aonpe__ports_4__stack_34l__width_34:mux_ild_ilc_curhdr_l , sii_ild_dpbuff_macro__dbuff_16x__stack_34c__width_34:buff_ipcc_data_out_h , sii_ild_dpbuff_macro__dbuff_16x__stack_36c__width_36:buff_ipcc_data_out_l , sii_ild_dpmsff_macro__stack_70c__width_70:ff_sii_l2t_hdr0 , sii_ild_dpmsff_macro__stack_70c__width_70:ff_sii_l2t_hdr1 , sii_ild_dpmsff_macro__stack_70c__width_70:ff_sii_l2t_hdr2 , sii_ild_dpmsff_macro__stack_70c__width_70:ff_sii_l2t_hdr3 
Instantiated by:sii:ild0 , sii:ild1 , sii:ild2 , sii:ild3 , sii:ild4 , sii:ild5 , sii:ild6 , sii:ild7 
 sii_ild_dpand_macro__left_0__ports_2__stack_4r__width_2
File:sii_ild_dp.v
Instantiates:and2:d0_0 
Instantiated by:sii_ild_dp:and_data_cyc_sel 
 sii_ild_dpbuff_macro__dbuff_16x__stack_34c__width_34
File:sii_ild_dp.v
Instantiates:buff:d0_0 
Instantiated by:sii_ild_dp:buff_ipcc_data_out_h 
 sii_ild_dpbuff_macro__dbuff_16x__stack_36c__width_36
File:sii_ild_dp.v
Instantiates:buff:d0_0 
Instantiated by:sii_ild_dp:buff_ipcc_data_out_l 
 sii_ild_dpcmp_macro__dcmp_8x__width_32
File:sii_ild_dp.v
Instantiates:cmp:m0_0 
Instantiated by:sii_ild_dp:cmp_81_64 
 sii_ild_dpcmp_macro__dcmp_8x__width_64
File:sii_ild_dp.v
Instantiates:cmp:m0_0 
Instantiated by:sii_ild_dp:cmp_63_0 
 sii_ild_dpinv_macro__width_2
File:sii_ild_dp.v
Instantiates:inv:d0_0 
Instantiated by:sii_ild_dp:inv_fail 
 sii_ild_dpmsff_macro__dmsff_32x__stack_32c__width_32
File:sii_ild_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sii_ild_dp:ff_sii_l2t_req 
 sii_ild_dpmsff_macro__stack_2c__width_2
File:sii_ild_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sii_ild_dp:ff_sii_mb0_ild_fail 
 sii_ild_dpmsff_macro__stack_70c__width_70
File:sii_ild_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sii_ild_dp:ff_sii_l2t_hdr0 , sii_ild_dp:ff_sii_l2t_hdr1 , sii_ild_dp:ff_sii_l2t_hdr2 , sii_ild_dp:ff_sii_l2t_hdr3 
 sii_ild_dpmsff_macro__stack_8c__width_8
File:sii_ild_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sii_ild_dp:ff_sii_mb0_wdata_rrr , sii_ild_dp:ff_sii_mb0_wdata_rr , sii_ild_dp:ff_sii_mb0_wdata_r , sii_ild_dp:ff_sii_l2b_ecc 
 sii_ild_dpmux_macro__dmux_8x__mux_aonpe__ports_4__stack_32l__width_32
File:sii_ild_dp.v
Instantiates:cl_dp1_muxbuff4_8x:c0_0 , mux4s:d0_0 
Instantiated by:sii_ild_dp:mux_sii_l2t_req 
 sii_ild_dpmux_macro__dmux_8x__mux_aonpe__ports_4__stack_34l__width_34
File:sii_ild_dp.v
Instantiates:cl_dp1_muxbuff4_8x:c0_0 , mux4s:d0_0 
Instantiated by:sii_ild_dp:mux_ild_ilc_curhdr_l 
 sii_ild_dpmux_macro__dmux_8x__mux_aonpe__ports_4__stack_36r__width_36
File:sii_ild_dp.v
Instantiates:cl_dp1_muxbuff4_8x:c0_0 , mux4s:d0_0 
Instantiated by:sii_ild_dp:mux_ild_ilc_curhdr_h 
 sii_ild_dpmux_macro__mux_aonpe__ports_2__stack_32r__width_8
File:sii_ild_dp.v
Instantiates:cl_dp1_muxbuff2_8x:c0_0 , mux2s:d0_0 
Instantiated by:sii_ild_dp:mux_sii_l2b_ecc_hdr , sii_ild_dp:mux_sii_l2b_ecc 
 sii_inc_ctl
File:sii_inc_ctl.v
Instantiates:sii_inc_ctll1clkhdr_ctl_macro:clkgen , sii_inc_ctlspare_ctl_macro__num_2:spares , sii_inc_ctlmsff_ctl_macro__width_5:reg_cstate , sii_inc_ctlmsff_ctl_macro__width_2:reg_sii_mb0_ind_fail , sii_inc_ctlmsff_ctl_macro__width_68:reg_mbist1_data_rr , sii_inc_ctlmsff_ctl_macro__width_68:reg_mbist1_data_r , sii_inc_ctlmsff_ctl_macro__width_1:reg_rd_ovfl , sii_inc_ctlmsff_ctl_macro__width_1:reg_got_gnt , sii_inc_ctlmsff_ctl_macro__width_1:reg_cmp_io_syn_en , sii_inc_ctlmsff_ctl_macro__width_1:reg_cmp_io_syn_en_dly2 , sii_inc_ctlmsff_ctl_macro__width_1:reg_cmp_io_syn_en_dly3 , sii_inc_ctlmsff_ctl_macro__en_1__width_1:reg_ncu_sii_gnt , sii_inc_ctlmsff_ctl_macro__width_3:reg_cyc_cnt_r , sii_inc_ctlmsff_ctl_macro__width_6:reg_inc_indq_rd_addr , sii_inc_ctlmsff_ctl_macro__en_1__width_1:reg_sii_ncu_req , sii_inc_ctlmsff_ctl_macro__en_1__width_32:reg_sii_ncu_data , sii_inc_ctlmsff_ctl_macro__en_1__width_2:reg_sii_ncu_dparity , sii_inc_ctlmsff_ctl_macro__width_1:reg_cmp_io_sync_en , sii_inc_ctlmsff_ctl_macro__width_1:reg_io_cmp_sync_en , sii_inc_ctlmsff_ctl_macro__width_1:reg_sii_mb0_run , sii_inc_ctlmsff_ctl_macro__width_1:reg_sii_mb0_ind_rd_en , sii_inc_ctlmsff_ctl_macro__width_6:reg_sii_mb0_addr , sii_inc_ctlmsff_ctl_macro__width_8:reg_sii_mb0_wdata , sii_inc_ctlmsff_ctl_macro__width_1:reg_ind_fifo_full 
Instantiated by:sii:inc 
 sii_inc_ctll1clkhdr_ctl_macro
File:sii_inc_ctl.v
Instantiates:cl_sc1_l1hdr_8x:c_0 
Instantiated by:sii_inc_ctl:clkgen 
 sii_inc_ctlmsff_ctl_macro__en_1__width_1
File:sii_inc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_inc_ctl:reg_ncu_sii_gnt , sii_inc_ctl:reg_sii_ncu_req 
 sii_inc_ctlmsff_ctl_macro__en_1__width_2
File:sii_inc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_inc_ctl:reg_sii_ncu_dparity 
 sii_inc_ctlmsff_ctl_macro__en_1__width_32
File:sii_inc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_inc_ctl:reg_sii_ncu_data 
 sii_inc_ctlmsff_ctl_macro__width_1
File:sii_inc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_inc_ctl:reg_rd_ovfl , sii_inc_ctl:reg_got_gnt , sii_inc_ctl:reg_cmp_io_syn_en , sii_inc_ctl:reg_cmp_io_syn_en_dly2 , sii_inc_ctl:reg_cmp_io_syn_en_dly3 , sii_inc_ctl:reg_cmp_io_sync_en , sii_inc_ctl:reg_io_cmp_sync_en , sii_inc_ctl:reg_sii_mb0_run , sii_inc_ctl:reg_sii_mb0_ind_rd_en , sii_inc_ctl:reg_ind_fifo_full 
 sii_inc_ctlmsff_ctl_macro__width_2
File:sii_inc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_inc_ctl:reg_sii_mb0_ind_fail 
 sii_inc_ctlmsff_ctl_macro__width_3
File:sii_inc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_inc_ctl:reg_cyc_cnt_r 
 sii_inc_ctlmsff_ctl_macro__width_5
File:sii_inc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_inc_ctl:reg_cstate 
 sii_inc_ctlmsff_ctl_macro__width_6
File:sii_inc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_inc_ctl:reg_inc_indq_rd_addr , sii_inc_ctl:reg_sii_mb0_addr 
 sii_inc_ctlmsff_ctl_macro__width_68
File:sii_inc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_inc_ctl:reg_mbist1_data_rr , sii_inc_ctl:reg_mbist1_data_r 
 sii_inc_ctlmsff_ctl_macro__width_8
File:sii_inc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_inc_ctl:reg_sii_mb0_wdata 
 sii_inc_ctlspare_ctl_macro__num_2
File:sii_inc_ctl.v
Instantiates:cl_sc1_msff_8x:spare0_flop , cl_u1_buf_32x:spare0_buf_32x , cl_u1_nand3_8x:spare0_nand3_8x , cl_u1_inv_8x:spare0_inv_8x , cl_u1_aoi22_4x:spare0_aoi22_4x , cl_u1_buf_8x:spare0_buf_8x , cl_u1_oai22_4x:spare0_oai22_4x , cl_u1_inv_16x:spare0_inv_16x , cl_u1_nand2_16x:spare0_nand2_16x , cl_u1_nor3_4x:spare0_nor3_4x , cl_u1_nand2_8x:spare0_nand2_8x , cl_u1_buf_16x:spare0_buf_16x , cl_u1_nor2_16x:spare0_nor2_16x , cl_u1_inv_32x:spare0_inv_32x , cl_sc1_msff_8x:spare1_flop , cl_u1_buf_32x:spare1_buf_32x , cl_u1_nand3_8x:spare1_nand3_8x , cl_u1_inv_8x:spare1_inv_8x , cl_u1_aoi22_4x:spare1_aoi22_4x , cl_u1_buf_8x:spare1_buf_8x , cl_u1_oai22_4x:spare1_oai22_4x , cl_u1_inv_16x:spare1_inv_16x , cl_u1_nand2_16x:spare1_nand2_16x , cl_u1_nor3_4x:spare1_nor3_4x , cl_u1_nand2_8x:spare1_nand2_8x , cl_u1_buf_16x:spare1_buf_16x , cl_u1_nor2_16x:spare1_nor2_16x , cl_u1_inv_32x:spare1_inv_32x 
Instantiated by:sii_inc_ctl:spares 
 sii_ipcc_ctl
File:sii_ipcc_ctl.v
Instantiates:sii_ipcc_ctll1clkhdr_ctl_macro:clkgen , cl_sc1_msff_8x:spare0_flop , cl_u1_buf_32x:spare0_buf_32x , cl_u1_nand3_8x:spare0_nand3_8x , cl_u1_inv_8x:spare0_inv_8x , cl_u1_aoi22_4x:spare0_aoi22_4x , cl_u1_buf_8x:spare0_buf_8x , cl_u1_oai22_4x:spare0_oai22_4x , cl_u1_inv_16x:spare0_inv_16x , cl_u1_nand2_16x:spare0_nand2_16x , cl_u1_nor3_4x:spare0_nor3_4x , cl_u1_nand2_8x:spare0_nand2_8x , cl_u1_buf_16x:spare0_buf_16x , cl_u1_nor2_16x:spare0_nor2_16x , cl_u1_inv_32x:spare0_inv_32x , cl_sc1_msff_8x:spare1_flop , cl_u1_buf_32x:spare1_buf_32x , cl_u1_nand3_8x:spare1_nand3_8x , cl_u1_inv_8x:spare1_inv_8x , cl_u1_aoi22_4x:spare1_aoi22_4x , cl_u1_buf_8x:spare1_buf_8x , cl_u1_oai22_4x:spare1_oai22_4x , cl_u1_inv_16x:spare1_inv_16x , cl_u1_nand2_16x:spare1_nand2_16x , cl_u1_nor3_4x:spare1_nor3_4x , cl_u1_nand2_8x:spare1_nand2_8x , cl_u1_buf_16x:spare1_buf_16x , cl_u1_nor2_16x:spare1_nor2_16x , cl_u1_inv_32x:spare1_inv_32x , cl_sc1_msff_8x:spare2_flop , cl_u1_buf_32x:spare2_buf_32x , cl_u1_nand3_8x:spare2_nand3_8x , cl_u1_inv_8x:spare2_inv_8x , cl_u1_aoi22_4x:spare2_aoi22_4x , cl_u1_buf_8x:spare2_buf_8x , cl_u1_oai22_4x:spare2_oai22_4x , cl_u1_inv_16x:spare2_inv_16x , cl_u1_nand2_16x:spare2_nand2_16x , cl_u1_nor3_4x:spare2_nor3_4x , cl_u1_nand2_8x:spare2_nand2_8x , cl_u1_buf_16x:spare2_buf_16x , cl_u1_nor2_16x:spare2_nor2_16x , cl_u1_inv_32x:spare2_inv_32x , cl_sc1_msff_8x:spare3_flop , cl_u1_buf_32x:spare3_buf_32x , cl_u1_nand3_8x:spare3_nand3_8x , cl_u1_inv_8x:spare3_inv_8x , cl_u1_aoi22_4x:spare3_aoi22_4x , cl_u1_buf_8x:spare3_buf_8x , cl_u1_oai22_4x:spare3_oai22_4x , cl_u1_inv_16x:spare3_inv_16x , cl_u1_nand2_16x:spare3_nand2_16x , cl_u1_nor3_4x:spare3_nor3_4x , cl_u1_nand2_8x:spare3_nand2_8x , cl_u1_buf_16x:spare3_buf_16x , cl_u1_nor2_16x:spare3_nor2_16x , cl_u1_inv_32x:spare3_inv_32x , cl_sc1_msff_8x:spare4_flop , cl_u1_buf_32x:spare4_buf_32x , cl_u1_nand3_8x:spare4_nand3_8x , cl_u1_inv_8x:spare4_inv_8x , cl_u1_aoi22_4x:spare4_aoi22_4x , cl_u1_buf_8x:spare4_buf_8x , cl_u1_oai22_4x:spare4_oai22_4x , cl_u1_inv_16x:spare4_inv_16x , cl_u1_nand2_16x:spare4_nand2_16x , cl_u1_nor3_4x:spare4_nor3_4x , cl_u1_nand2_8x:spare4_nand2_8x , cl_u1_buf_16x:spare4_buf_16x , cl_u1_nor2_16x:spare4_nor2_16x , cl_u1_inv_32x:spare4_inv_32x , cl_sc1_msff_8x:spare5_flop , cl_u1_buf_32x:spare5_buf_32x , cl_u1_nand3_8x:spare5_nand3_8x , cl_u1_inv_8x:spare5_inv_8x , cl_u1_aoi22_4x:spare5_aoi22_4x , cl_u1_buf_8x:spare5_buf_8x , cl_u1_oai22_4x:spare5_oai22_4x , cl_u1_inv_16x:spare5_inv_16x , cl_u1_nand2_16x:spare5_nand2_16x , cl_u1_nor3_4x:spare5_nor3_4x , cl_u1_nand2_8x:spare5_nand2_8x , cl_u1_buf_16x:spare5_buf_16x , cl_u1_nor2_16x:spare5_nor2_16x , cl_u1_inv_32x:spare5_inv_32x , cl_sc1_msff_8x:spare6_flop , cl_u1_buf_32x:spare6_buf_32x , cl_u1_nand3_8x:spare6_nand3_8x , cl_u1_inv_8x:spare6_inv_8x , cl_u1_aoi22_4x:spare6_aoi22_4x , cl_u1_buf_8x:spare6_buf_8x , cl_u1_oai22_4x:spare6_oai22_4x , cl_u1_inv_16x:spare6_inv_16x , cl_u1_nand2_16x:spare6_nand2_16x , cl_u1_nor3_4x:spare6_nor3_4x , cl_u1_nand2_8x:spare6_nand2_8x , cl_u1_buf_16x:spare6_buf_16x , cl_u1_nor2_16x:spare6_nor2_16x , cl_u1_inv_32x:spare6_inv_32x , cl_sc1_msff_8x:spare7_flop , cl_u1_buf_32x:spare7_buf_32x , cl_u1_nand3_8x:spare7_nand3_8x , cl_u1_inv_8x:spare7_inv_8x , cl_u1_aoi22_4x:spare7_aoi22_4x , cl_u1_buf_8x:spare7_buf_8x , cl_u1_oai22_4x:spare7_oai22_4x , cl_u1_inv_16x:spare7_inv_16x , cl_u1_nand2_16x:spare7_nand2_16x , cl_u1_nor3_4x:spare7_nor3_4x , cl_u1_nand2_8x:spare7_nand2_8x , cl_u1_buf_16x:spare7_buf_16x , cl_u1_nor2_16x:spare7_nor2_16x , cl_u1_inv_32x:spare7_inv_32x , cl_sc1_msff_8x:spare8_flop , cl_u1_buf_32x:spare8_buf_32x , cl_u1_nand3_8x:spare8_nand3_8x , cl_u1_inv_8x:spare8_inv_8x , cl_u1_aoi22_4x:spare8_aoi22_4x , cl_u1_buf_8x:spare8_buf_8x , cl_u1_oai22_4x:spare8_oai22_4x , cl_u1_inv_16x:spare8_inv_16x , cl_u1_nand2_16x:spare8_nand2_16x , cl_u1_nor3_4x:spare8_nor3_4x , cl_u1_nand2_8x:spare8_nand2_8x , cl_u1_buf_16x:spare8_buf_16x , cl_u1_nor2_16x:spare8_nor2_16x , cl_u1_inv_32x:spare8_inv_32x , cl_sc1_msff_8x:spare9_flop , cl_u1_buf_32x:spare9_buf_32x , cl_u1_nand3_8x:spare9_nand3_8x , cl_u1_inv_8x:spare9_inv_8x , cl_u1_aoi22_4x:spare9_aoi22_4x , cl_u1_buf_8x:spare9_buf_8x , cl_u1_oai22_4x:spare9_oai22_4x , cl_u1_inv_16x:spare9_inv_16x , cl_u1_nand2_16x:spare9_nand2_16x , cl_u1_nor3_4x:spare9_nor3_4x , cl_u1_nand2_8x:spare9_nand2_8x , cl_u1_buf_16x:spare9_buf_16x , cl_u1_nor2_16x:spare9_nor2_16x , cl_u1_inv_32x:spare9_inv_32x , sii_ipcc_ctlmsff_ctl_macro__en_1__width_5:reg_gnt , sii_ipcc_ctlmsff_ctl_macro__en_1__width_5:reg_gnt0 , sii_ipcc_ctlmsff_ctl_macro__width_14:reg_cstate , sii_ipcc_ctlmsff_ctl_macro__en_1__width_56:reg_err_ctag_pa , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_dma_wr , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_wrm , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_l2_io , sii_ipcc_ctlmsff_ctl_macro__width_5:reg_dmu_or_cnt , sii_ipcc_ctlmsff_ctl_macro__width_5:reg_dmu_by_cnt , sii_ipcc_ctlmsff_ctl_macro__width_5:reg_niu_or_cnt , sii_ipcc_ctlmsff_ctl_macro__width_5:reg_niu_by_cnt , sii_ipcc_ctlmsff_ctl_macro__width_6:reg_indq_wr_addr , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_indq_wr_en , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_indq_wr_en_dly , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_indq_wr_ovfl , sii_ipcc_ctlmsff_ctl_macro__width_2:reg_arb1 , sii_ipcc_ctlmsff_ctl_macro__width_4:reg_dmu_wrm_cnt , sii_ipcc_ctlmsff_ctl_macro__width_4:reg_niu_wrm_cnt , sii_ipcc_ctlmsff_ctl_macro__width_2:reg_dmu_or_wr_cnt , sii_ipcc_ctlmsff_ctl_macro__width_4:reg_dmu_by_wr_cnt , sii_ipcc_ctlmsff_ctl_macro__width_2:reg_niu_or_wr_cnt , sii_ipcc_ctlmsff_ctl_macro__width_4:reg_niu_by_wr_cnt , sii_ipcc_ctlmsff_ctl_macro__width_4:reg_niu_by_wr_cnt_snap , sii_ipcc_ctlmsff_ctl_macro__dmsff_32x__width_5:reg_ildq_wr_addr0 , sii_ipcc_ctlmsff_ctl_macro__dmsff_32x__width_5:reg_ildq_wr_addr1 , sii_ipcc_ctlmsff_ctl_macro__dmsff_32x__width_5:reg_ildq_wr_addr2 , sii_ipcc_ctlmsff_ctl_macro__dmsff_32x__width_5:reg_ildq_wr_addr3 , sii_ipcc_ctlmsff_ctl_macro__dmsff_32x__width_5:reg_ildq_wr_addr4 , sii_ipcc_ctlmsff_ctl_macro__dmsff_32x__width_5:reg_ildq_wr_addr5 , sii_ipcc_ctlmsff_ctl_macro__dmsff_32x__width_5:reg_ildq_wr_addr6 , sii_ipcc_ctlmsff_ctl_macro__dmsff_32x__width_5:reg_ildq_wr_addr7 , sii_ipcc_ctlmsff_ctl_macro__width_4:reg_ipdohq0_rd_addr , sii_ipcc_ctlmsff_ctl_macro__width_4:reg_ipdbhq0_rd_addr , sii_ipcc_ctlmsff_ctl_macro__width_4:reg_ipdohq1_rd_addr , sii_ipcc_ctlmsff_ctl_macro__width_4:reg_ipdbhq1_rd_addr , sii_ipcc_ctlmsff_ctl_macro__width_6:reg_ipdodq0_rd_addr , sii_ipcc_ctlmsff_ctl_macro__width_6:reg_ipdbdq0_rd_addr , sii_ipcc_ctlmsff_ctl_macro__width_6:reg_ipdodq1_rd_addr , sii_ipcc_ctlmsff_ctl_macro__width_6:reg_ipdbdq1_rd_addr , sii_ipcc_ctlmsff_ctl_macro__en_1__width_3:reg_curbank , sii_ipcc_ctlmsff_ctl_macro__en_1__width_4:reg_dmu_tag , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_ipcc_ipcs_dmu_wrack_p_pre , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_ipcc_ilc_cmd0 , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_ipcc_ilc_cmd1 , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_ipcc_ilc_cmd2 , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_ipcc_ilc_cmd3 , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_ipcc_ilc_cmd4 , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_ipcc_ilc_cmd5 , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_ipcc_ilc_cmd6 , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_ipcc_ilc_cmd7 , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_ipcc_ildq_wr_en0 , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_ipcc_ildq_wr_en1 , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_ipcc_ildq_wr_en2 , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_ipcc_ildq_wr_en3 , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_ipcc_ildq_wr_en4 , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_ipcc_ildq_wr_en5 , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_ipcc_ildq_wr_en6 , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_ipcc_ildq_wr_en7 , sii_ipcc_ctlmsff_ctl_macro__width_2:reg_arb1_hist , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_dmu_hist , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_niu_hist , sii_ipcc_ctlmsff_ctl_macro__width_64:reg_syndrome , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_sending , sii_ipcc_ctlmsff_ctl_macro__width_7:reg_send_cnt , sii_ipcc_ctlmsff_ctl_macro__width_6:reg_err_sig , sii_ipcc_ctlmsff_ctl_macro__width_128:reg_tcu_serial_data , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_tcu_go , sii_ipcc_ctlmsff_ctl_macro__width_8:reg_tcu_rcv_cnt , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_tcu_txfr_start , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_cmp_io_sync_en , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_io_cmp_sync_en , sii_ipcc_ctlmsff_ctl_macro__en_1__width_4:reg_sii_ncu_syn_data , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_sii_ncu_syn_vld , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_dmuctag_ue_r , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_dmuctag_ue , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_dmuctag_ce_r , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_dmuctag_ce , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_dmua_pe_r , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_dmua_pe , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_dmu_de_r , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_dmu_de , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_niuctag_ue_r , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_niuctag_ue , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_niuctag_ce_r , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_niuctag_ce , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_niua_pe_r , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_niua_pe , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_niu_de_r , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_niu_de , sii_ipcc_ctlmsff_ctl_macro__en_1__width_4:reg_ipcs_ipdohq0_wr_addr , sii_ipcc_ctlmsff_ctl_macro__en_1__width_4:reg_ipcs_ipdbhq0_wr_addr , sii_ipcc_ctlmsff_ctl_macro__en_1__width_6:reg_ipcs_ipdodq0_wr_addr , sii_ipcc_ctlmsff_ctl_macro__en_1__width_6:reg_ipcs_ipdbdq0_wr_addr , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_ipcs_ipdohq0_wr_en , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_ipcs_ipdbhq0_wr_en , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_ipcs_ipdodq0_wr_en , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_ipcs_ipdbdq0_wr_en , sii_ipcc_ctlmsff_ctl_macro__en_1__width_4:reg_ipcs_ipdohq1_wr_addr , sii_ipcc_ctlmsff_ctl_macro__en_1__width_4:reg_ipcs_ipdbhq1_wr_addr , sii_ipcc_ctlmsff_ctl_macro__en_1__width_6:reg_ipcs_ipdodq1_wr_addr , sii_ipcc_ctlmsff_ctl_macro__en_1__width_6:reg_ipcs_ipdbdq1_wr_addr , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_ipcs_ipdohq1_wr_en , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_ipcs_ipdbhq1_wr_en , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_ipcs_ipdodq1_wr_en , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_ipcs_ipdbdq1_wr_en , sii_ipcc_ctlmsff_ctl_macro__en_1__width_16:reg_ipcs_ipcc_dmu_or_dep , sii_ipcc_ctlmsff_ctl_macro__en_1__width_16:reg_ipcs_ipcc_dmu_by_dep , sii_ipcc_ctlmsff_ctl_macro__en_1__width_16:reg_ipcs_ipcc_niu_or_dep , sii_ipcc_ctlmsff_ctl_macro__en_1__width_16:reg_ipcs_ipcc_niu_by_dep , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_add_dmu_or , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_add_dmu_by , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_add_niu_or , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_add_niu_by , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_ncu_sii_pm , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_ncu_sii_ba01 , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_ncu_sii_ba23 , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_ncu_sii_ba45 , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_ncu_sii_ba67 , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_ncu_sii_l2_idx_hash_en , sii_ipcc_ctlmsff_ctl_macro__en_1__width_4:reg_ipcc_ipcs_dmu_tag , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_ipcc_ipcs_wrack_lv , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_ipcc_ipcs_dmu_wrack_p , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_wrack_lv , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_dmu_wrm_mode , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_niu_wrm_mode , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_dmu_or_dq_pre , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_dmu_or_dq , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_dmu_by_dq_pre , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_dmu_by_dq , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_niu_or_dq_pre , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_niu_or_dq , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_niu_by_dq_pre , sii_ipcc_ctlmsff_ctl_macro__en_1__width_1:reg_niu_by_dq , sii_ipcc_ctlmsff_ctl_macro__width_4:reg_sync_dmu_or_rd_ptr_pre , sii_ipcc_ctlmsff_ctl_macro__en_1__width_4:reg_sync_dmu_or_rd_ptr , sii_ipcc_ctlmsff_ctl_macro__width_4:reg_sync_dmu_by_rd_ptr_pre , sii_ipcc_ctlmsff_ctl_macro__en_1__width_4:reg_sync_dmu_by_rd_ptr , sii_ipcc_ctlmsff_ctl_macro__width_4:reg_sync_niu_or_rd_ptr_pre , sii_ipcc_ctlmsff_ctl_macro__en_1__width_4:reg_sync_niu_or_rd_ptr , sii_ipcc_ctlmsff_ctl_macro__width_4:reg_sync_niu_by_rd_ptr_pre , sii_ipcc_ctlmsff_ctl_macro__en_1__width_4:reg_sync_niu_by_rd_ptr , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_sii_mb1_run , sii_ipcc_ctlmsff_ctl_macro__width_6:reg_sii_mb1_addr , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_sii_mb1_ipdohq0_rd_en , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_sii_mb1_ipdbhq0_rd_en , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_sii_mb1_ipdodq0_rd_en , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_sii_mb1_ipdbdq0_rd_en , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_sii_mb1_ipdohq1_rd_en , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_sii_mb1_ipdbhq1_rd_en , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_sii_mb1_ipdodq1_rd_en , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_sii_mb1_ipdbdq1_rd_en , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_sii_mb0_run , sii_ipcc_ctlmsff_ctl_macro__width_6:reg_sii_mb0_addr , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_sii_mb0_wr_en , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_sii_mb0_ind_wr_en , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_tcu_sii_data , sii_ipcc_ctlmsff_ctl_macro__width_1:reg_tcu_sii_vld 
Instantiated by:sii:ipcc 
 sii_ipcc_ctll1clkhdr_ctl_macro
File:sii_ipcc_ctl.v
Instantiates:cl_sc1_l1hdr_8x:c_0 
Instantiated by:sii_ipcc_ctl:clkgen 
 sii_ipcc_ctlmsff_ctl_macro__dmsff_32x__width_5
File:sii_ipcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcc_ctl:reg_ildq_wr_addr0 , sii_ipcc_ctl:reg_ildq_wr_addr1 , sii_ipcc_ctl:reg_ildq_wr_addr2 , sii_ipcc_ctl:reg_ildq_wr_addr3 , sii_ipcc_ctl:reg_ildq_wr_addr4 , sii_ipcc_ctl:reg_ildq_wr_addr5 , sii_ipcc_ctl:reg_ildq_wr_addr6 , sii_ipcc_ctl:reg_ildq_wr_addr7 
 sii_ipcc_ctlmsff_ctl_macro__en_1__width_1
File:sii_ipcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcc_ctl:reg_l2_io , sii_ipcc_ctl:reg_ipcc_ipcs_dmu_wrack_p_pre , sii_ipcc_ctl:reg_sii_ncu_syn_vld , sii_ipcc_ctl:reg_dmuctag_ue , sii_ipcc_ctl:reg_dmuctag_ce , sii_ipcc_ctl:reg_dmua_pe , sii_ipcc_ctl:reg_dmu_de , sii_ipcc_ctl:reg_niuctag_ue , sii_ipcc_ctl:reg_niuctag_ce , sii_ipcc_ctl:reg_niua_pe , sii_ipcc_ctl:reg_niu_de , sii_ipcc_ctl:reg_ipcs_ipdohq0_wr_en , sii_ipcc_ctl:reg_ipcs_ipdbhq0_wr_en , sii_ipcc_ctl:reg_ipcs_ipdodq0_wr_en , sii_ipcc_ctl:reg_ipcs_ipdbdq0_wr_en , sii_ipcc_ctl:reg_ipcs_ipdohq1_wr_en , sii_ipcc_ctl:reg_ipcs_ipdbhq1_wr_en , sii_ipcc_ctl:reg_ipcs_ipdodq1_wr_en , sii_ipcc_ctl:reg_ipcs_ipdbdq1_wr_en , sii_ipcc_ctl:reg_add_dmu_or , sii_ipcc_ctl:reg_add_dmu_by , sii_ipcc_ctl:reg_add_niu_or , sii_ipcc_ctl:reg_add_niu_by , sii_ipcc_ctl:reg_ncu_sii_pm , sii_ipcc_ctl:reg_ncu_sii_ba01 , sii_ipcc_ctl:reg_ncu_sii_ba23 , sii_ipcc_ctl:reg_ncu_sii_ba45 , sii_ipcc_ctl:reg_ncu_sii_ba67 , sii_ipcc_ctl:reg_ncu_sii_l2_idx_hash_en , sii_ipcc_ctl:reg_ipcc_ipcs_wrack_lv , sii_ipcc_ctl:reg_ipcc_ipcs_dmu_wrack_p , sii_ipcc_ctl:reg_dmu_or_dq , sii_ipcc_ctl:reg_dmu_by_dq , sii_ipcc_ctl:reg_niu_or_dq , sii_ipcc_ctl:reg_niu_by_dq 
 sii_ipcc_ctlmsff_ctl_macro__en_1__width_16
File:sii_ipcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcc_ctl:reg_ipcs_ipcc_dmu_or_dep , sii_ipcc_ctl:reg_ipcs_ipcc_dmu_by_dep , sii_ipcc_ctl:reg_ipcs_ipcc_niu_or_dep , sii_ipcc_ctl:reg_ipcs_ipcc_niu_by_dep 
 sii_ipcc_ctlmsff_ctl_macro__en_1__width_3
File:sii_ipcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcc_ctl:reg_curbank 
 sii_ipcc_ctlmsff_ctl_macro__en_1__width_4
File:sii_ipcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcc_ctl:reg_dmu_tag , sii_ipcc_ctl:reg_sii_ncu_syn_data , sii_ipcc_ctl:reg_ipcs_ipdohq0_wr_addr , sii_ipcc_ctl:reg_ipcs_ipdbhq0_wr_addr , sii_ipcc_ctl:reg_ipcs_ipdohq1_wr_addr , sii_ipcc_ctl:reg_ipcs_ipdbhq1_wr_addr , sii_ipcc_ctl:reg_ipcc_ipcs_dmu_tag , sii_ipcc_ctl:reg_sync_dmu_or_rd_ptr , sii_ipcc_ctl:reg_sync_dmu_by_rd_ptr , sii_ipcc_ctl:reg_sync_niu_or_rd_ptr , sii_ipcc_ctl:reg_sync_niu_by_rd_ptr 
 sii_ipcc_ctlmsff_ctl_macro__en_1__width_5
File:sii_ipcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcc_ctl:reg_gnt , sii_ipcc_ctl:reg_gnt0 
 sii_ipcc_ctlmsff_ctl_macro__en_1__width_56
File:sii_ipcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcc_ctl:reg_err_ctag_pa 
 sii_ipcc_ctlmsff_ctl_macro__en_1__width_6
File:sii_ipcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcc_ctl:reg_ipcs_ipdodq0_wr_addr , sii_ipcc_ctl:reg_ipcs_ipdbdq0_wr_addr , sii_ipcc_ctl:reg_ipcs_ipdodq1_wr_addr , sii_ipcc_ctl:reg_ipcs_ipdbdq1_wr_addr 
 sii_ipcc_ctlmsff_ctl_macro__width_1
File:sii_ipcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcc_ctl:reg_dma_wr , sii_ipcc_ctl:reg_wrm , sii_ipcc_ctl:reg_indq_wr_en , sii_ipcc_ctl:reg_indq_wr_en_dly , sii_ipcc_ctl:reg_indq_wr_ovfl , sii_ipcc_ctl:reg_ipcc_ilc_cmd0 , sii_ipcc_ctl:reg_ipcc_ilc_cmd1 , sii_ipcc_ctl:reg_ipcc_ilc_cmd2 , sii_ipcc_ctl:reg_ipcc_ilc_cmd3 , sii_ipcc_ctl:reg_ipcc_ilc_cmd4 , sii_ipcc_ctl:reg_ipcc_ilc_cmd5 , sii_ipcc_ctl:reg_ipcc_ilc_cmd6 , sii_ipcc_ctl:reg_ipcc_ilc_cmd7 , sii_ipcc_ctl:reg_ipcc_ildq_wr_en0 , sii_ipcc_ctl:reg_ipcc_ildq_wr_en1 , sii_ipcc_ctl:reg_ipcc_ildq_wr_en2 , sii_ipcc_ctl:reg_ipcc_ildq_wr_en3 , sii_ipcc_ctl:reg_ipcc_ildq_wr_en4 , sii_ipcc_ctl:reg_ipcc_ildq_wr_en5 , sii_ipcc_ctl:reg_ipcc_ildq_wr_en6 , sii_ipcc_ctl:reg_ipcc_ildq_wr_en7 , sii_ipcc_ctl:reg_dmu_hist , sii_ipcc_ctl:reg_niu_hist , sii_ipcc_ctl:reg_sending , sii_ipcc_ctl:reg_tcu_go , sii_ipcc_ctl:reg_tcu_txfr_start , sii_ipcc_ctl:reg_cmp_io_sync_en , sii_ipcc_ctl:reg_io_cmp_sync_en , sii_ipcc_ctl:reg_dmuctag_ue_r , sii_ipcc_ctl:reg_dmuctag_ce_r , sii_ipcc_ctl:reg_dmua_pe_r , sii_ipcc_ctl:reg_dmu_de_r , sii_ipcc_ctl:reg_niuctag_ue_r , sii_ipcc_ctl:reg_niuctag_ce_r , sii_ipcc_ctl:reg_niua_pe_r , sii_ipcc_ctl:reg_niu_de_r , sii_ipcc_ctl:reg_wrack_lv , sii_ipcc_ctl:reg_dmu_wrm_mode , sii_ipcc_ctl:reg_niu_wrm_mode , sii_ipcc_ctl:reg_dmu_or_dq_pre , sii_ipcc_ctl:reg_dmu_by_dq_pre , sii_ipcc_ctl:reg_niu_or_dq_pre , sii_ipcc_ctl:reg_niu_by_dq_pre , sii_ipcc_ctl:reg_sii_mb1_run , sii_ipcc_ctl:reg_sii_mb1_ipdohq0_rd_en , sii_ipcc_ctl:reg_sii_mb1_ipdbhq0_rd_en , sii_ipcc_ctl:reg_sii_mb1_ipdodq0_rd_en , sii_ipcc_ctl:reg_sii_mb1_ipdbdq0_rd_en , sii_ipcc_ctl:reg_sii_mb1_ipdohq1_rd_en , sii_ipcc_ctl:reg_sii_mb1_ipdbhq1_rd_en , sii_ipcc_ctl:reg_sii_mb1_ipdodq1_rd_en , sii_ipcc_ctl:reg_sii_mb1_ipdbdq1_rd_en , sii_ipcc_ctl:reg_sii_mb0_run , sii_ipcc_ctl:reg_sii_mb0_wr_en , sii_ipcc_ctl:reg_sii_mb0_ind_wr_en , sii_ipcc_ctl:reg_tcu_sii_data , sii_ipcc_ctl:reg_tcu_sii_vld 
 sii_ipcc_ctlmsff_ctl_macro__width_128
File:sii_ipcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcc_ctl:reg_tcu_serial_data 
 sii_ipcc_ctlmsff_ctl_macro__width_14
File:sii_ipcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcc_ctl:reg_cstate 
 sii_ipcc_ctlmsff_ctl_macro__width_2
File:sii_ipcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcc_ctl:reg_arb1 , sii_ipcc_ctl:reg_dmu_or_wr_cnt , sii_ipcc_ctl:reg_niu_or_wr_cnt , sii_ipcc_ctl:reg_arb1_hist 
 sii_ipcc_ctlmsff_ctl_macro__width_4
File:sii_ipcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcc_ctl:reg_dmu_wrm_cnt , sii_ipcc_ctl:reg_niu_wrm_cnt , sii_ipcc_ctl:reg_dmu_by_wr_cnt , sii_ipcc_ctl:reg_niu_by_wr_cnt , sii_ipcc_ctl:reg_niu_by_wr_cnt_snap , sii_ipcc_ctl:reg_ipdohq0_rd_addr , sii_ipcc_ctl:reg_ipdbhq0_rd_addr , sii_ipcc_ctl:reg_ipdohq1_rd_addr , sii_ipcc_ctl:reg_ipdbhq1_rd_addr , sii_ipcc_ctl:reg_sync_dmu_or_rd_ptr_pre , sii_ipcc_ctl:reg_sync_dmu_by_rd_ptr_pre , sii_ipcc_ctl:reg_sync_niu_or_rd_ptr_pre , sii_ipcc_ctl:reg_sync_niu_by_rd_ptr_pre 
 sii_ipcc_ctlmsff_ctl_macro__width_5
File:sii_ipcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcc_ctl:reg_dmu_or_cnt , sii_ipcc_ctl:reg_dmu_by_cnt , sii_ipcc_ctl:reg_niu_or_cnt , sii_ipcc_ctl:reg_niu_by_cnt 
 sii_ipcc_ctlmsff_ctl_macro__width_6
File:sii_ipcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcc_ctl:reg_indq_wr_addr , sii_ipcc_ctl:reg_ipdodq0_rd_addr , sii_ipcc_ctl:reg_ipdbdq0_rd_addr , sii_ipcc_ctl:reg_ipdodq1_rd_addr , sii_ipcc_ctl:reg_ipdbdq1_rd_addr , sii_ipcc_ctl:reg_err_sig , sii_ipcc_ctl:reg_sii_mb1_addr , sii_ipcc_ctl:reg_sii_mb0_addr 
 sii_ipcc_ctlmsff_ctl_macro__width_64
File:sii_ipcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcc_ctl:reg_syndrome 
 sii_ipcc_ctlmsff_ctl_macro__width_7
File:sii_ipcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcc_ctl:reg_send_cnt 
 sii_ipcc_ctlmsff_ctl_macro__width_8
File:sii_ipcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcc_ctl:reg_tcu_rcv_cnt 
 sii_ipcc_dp
File:sii_ipcc_dp.v
Instantiates:sii_ipcc_dpmux_macro__mux_pgpe__ports_2__stack_64c__width_64:mux_ipcc_data_63_0 , sii_ipcc_dpmux_macro__mux_pgpe__ports_2__stack_20c__width_20:mux_ipcc_data_81_64 , sii_ipcc_dpbuff_macro__dbuff_48x__stack_46c__width_46:buff_ipcc_data_all0_45_0 , sii_ipcc_dpbuff_macro__dbuff_48x__stack_44c__width_44:buff_ipcc_data_all0_89_46 , sii_ipcc_dpbuff_macro__dbuff_48x__stack_46c__width_46:buff_ipcc_data_all1_45_0 , sii_ipcc_dpbuff_macro__dbuff_48x__stack_44c__width_44:buff_ipcc_data_all1_89_46 , sii_ipcc_dpbuff_macro__dbuff_48x__stack_46c__width_46:buff_ipcc_data_all2_45_0 , sii_ipcc_dpbuff_macro__dbuff_48x__stack_44c__width_44:buff_ipcc_data_all2_89_46 , sii_ipcc_dpbuff_macro__dbuff_48x__stack_46c__width_46:buff_ipcc_data_all3_45_0 , sii_ipcc_dpbuff_macro__dbuff_48x__stack_44c__width_44:buff_ipcc_data_all3_89_46 , sii_ipcc_dpmsff_macro__stack_72c__width_72:ff_ipcc_data_out , sii_ipcc_dpmux_macro__mux_pgpe__ports_2__stack_8c__width_8:mux_ipcc_data_out_71_64 , sii_ipcc_dpmux_macro__mux_pgnpe__ports_3__stack_64c__width_64:mux_ipcc_data_out_63_0 , sii_ipcc_dpinv_macro__stack_2r__width_2:inv_hdr_data_sel_curhdr58 , sii_ipcc_dpand_macro__left_0__ports_2__stack_2r__width_2:and_hdr_sel , sii_ipcc_dpinv_macro__stack_72r__width_72:inv_curhdr , sii_ipcc_dpmsffi_macro__stack_72c__width_72:ff_curhdri , sii_ipcc_dpbuff_macro__minbuff_1__width_8:buf_curhdr_72_64 , sii_ipcc_dpbuff_macro__minbuff_1__width_64:buf_curhdr_63_0 , sii_ipcc_dpinv_macro__left_0__stack_4r__width_4:inv_gnt0_r_m , sii_ipcc_dpnor_macro__left_0__ports_3__stack_2r__width_1:nor_gnt0_2 , sii_ipcc_dpand_macro__left_0__ports_2__stack_4r__width_1:and_gnt1 , sii_ipcc_dpand_macro__left_0__ports_3__stack_4r__width_1:and_gnt2 , sii_ipcc_dpand_macro__left_0__ports_4__stack_4r__width_1:and_gnt3 , sii_ipcc_dpand_macro__left_0__ports_3__stack_4r__width_1:and_gnt4 , sii_ipcc_dpmux_macro__mux_pgnpe__ports_5__stack_72c__width_72:mux_curhdr , sii_ipcc_dpmsff_macro__stack_64c__width_64:ff_newdata , sii_ipcc_dpmux_macro__mux_pgpe__ports_2__stack_64c__width_64:mux_newdata , sii_ipcc_dpmux_macro__mux_pgdec__ports_8__stack_64c__width_64:mux_newdata_tmp , sii_ipcc_dpmsff_macro__stack_14c__width_14:ff_newbe_par , sii_ipcc_dpmsff_macro__stack_14c__width_14:ff_newbe_par_rr , sii_ipcc_dpmsff_macro__stack_8c__width_8:ff_mb0_wdata , sii_ipcc_dpbuff_macro__minbuff_1__stack_8r__width_8:buf_sii_mb0_wdata , sii_ipcc_dpmux_macro__mux_pgpe__ports_2__stack_14c__width_14:mux_ipcc_ecc , sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4:xor_ecc , sii_ipcc_dpxor_macro__ports_2__stack_10r__width_9:xor_ecch_0_l1 , sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4:xor_ecch_0_l2 , sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2:xor_ecch_0_l3 , sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1:xor_ecch_0_l4 , sii_ipcc_dpxor_macro__ports_2__stack_10r__width_9:xor_ecch_1_l1 , sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4:xor_ecch_1_l2 , sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2:xor_ecch_1_l3 , sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1:xor_ecch_1_l4 , sii_ipcc_dpxor_macro__ports_2__stack_10r__width_9:xor_ecch_2_l1 , sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4:xor_ecch_2_l2 , sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2:xor_ecch_2_l3 , sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1:xor_ecch_2_l4 , sii_ipcc_dpxor_macro__ports_2__stack_8r__width_7:xor_ecch_3_l1 , sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4:xor_ecch_3_l2 , sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2:xor_ecch_3_l3 , sii_ipcc_dpxor_macro__ports_2__stack_2r__width_1:xor_ecch_3_l4 , sii_ipcc_dpxor_macro__ports_2__stack_8r__width_7:xor_ecch_4_l1 , sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4:xor_ecch_4_l2 , sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2:xor_ecch_4_l3 , sii_ipcc_dpxor_macro__ports_2__stack_2r__width_1:xor_ecch_4_l4 , sii_ipcc_dpxor_macro__ports_2__stack_4r__width_3:xor_ecch_5_l1 , sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1:xor_ecch_5_l4 , sii_ipcc_dpxor_macro__ports_2__stack_10r__width_9:xor_ecch_6_l1 , sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4:xor_ecch_6_l2 , sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2:xor_ecch_6_l3 , sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1:xor_ecch_6_l4 , sii_ipcc_dpxor_macro__ports_2__stack_10r__width_9:xor_eccl_0_l1 , sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4:xor_eccl_0_l2 , sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2:xor_eccl_0_l3 , sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1:xor_eccl_0_l4 , sii_ipcc_dpxor_macro__ports_2__stack_10r__width_9:xor_eccl_1_l1 , sii_ipcc_dpxor_macro__ports_2__stack_8r__width_4:xor_eccl_1_l2 , sii_ipcc_dpxor_macro__ports_2__stack_4r__width_2:xor_eccl_1_l3 , sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1:xor_eccl_1_l4 , sii_ipcc_dpxor_macro__ports_2__stack_10r__width_9:xor_eccl_2_l1 , sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4:xor_eccl_2_l2 , sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2:xor_eccl_2_l3 , sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1:xor_eccl_2_l4 , sii_ipcc_dpxor_macro__ports_2__stack_8r__width_7:xor_eccl_3_l1 , sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4:xor_eccl_3_l2 , sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2:xor_eccl_3_l3 , sii_ipcc_dpxor_macro__ports_2__stack_2r__width_1:xor_eccl_3_l4 , sii_ipcc_dpxor_macro__ports_2__stack_8r__width_7:xor_eccl_4_l1 , sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4:xor_eccl_4_l2 , sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2:xor_eccl_4_l3 , sii_ipcc_dpxor_macro__ports_2__stack_2r__width_1:xor_eccl_4_l4 , sii_ipcc_dpxor_macro__ports_2__stack_4r__width_3:xor_eccl_5_l1 , sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1:xor_eccl_5_l4 , sii_ipcc_dpxor_macro__ports_2__stack_10r__width_9:xor_eccl_6_l1 , sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4:xor_eccl_6_l2 , sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2:xor_eccl_6_l3 , sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1:xor_eccl_6_l4 , sii_ipcc_dpmux_macro__mux_pgpe__ports_2__stack_14c__width_14:mux_newbe_par , sii_ipcc_dpmux_macro__mux_pgdec__ports_8__stack_14c__width_14:mux_newbe_par1 , sii_ipcc_dpmsff_macro__stack_18c__width_18:ff_newbe , sii_ipcc_dpmux_macro__mux_pgdec__ports_4__stack_18c__width_18:mux_newbe , sii_ipcc_dpmsff_macro__stack_14c__width_14:ff_ipcc_ecc 
Instantiated by:sii:ipcc_dp 
 sii_ipcc_dpand_macro__left_0__ports_2__stack_2r__width_2
File:sii_ipcc_dp.v
Instantiates:and2:d0_0 
Instantiated by:sii_ipcc_dp:and_hdr_sel 
 sii_ipcc_dpand_macro__left_0__ports_2__stack_4r__width_1
File:sii_ipcc_dp.v
Instantiates:and2:d0_0 
Instantiated by:sii_ipcc_dp:and_gnt1 
 sii_ipcc_dpand_macro__left_0__ports_3__stack_4r__width_1
File:sii_ipcc_dp.v
Instantiates:and3:d0_0 
Instantiated by:sii_ipcc_dp:and_gnt2 , sii_ipcc_dp:and_gnt4 
 sii_ipcc_dpand_macro__left_0__ports_4__stack_4r__width_1
File:sii_ipcc_dp.v
Instantiates:and4:d0_0 
Instantiated by:sii_ipcc_dp:and_gnt3 
 sii_ipcc_dpbuff_macro__dbuff_48x__stack_44c__width_44
File:sii_ipcc_dp.v
Instantiates:buff:d0_0 
Instantiated by:sii_ipcc_dp:buff_ipcc_data_all0_89_46 , sii_ipcc_dp:buff_ipcc_data_all1_89_46 , sii_ipcc_dp:buff_ipcc_data_all2_89_46 , sii_ipcc_dp:buff_ipcc_data_all3_89_46 
 sii_ipcc_dpbuff_macro__dbuff_48x__stack_46c__width_46
File:sii_ipcc_dp.v
Instantiates:buff:d0_0 
Instantiated by:sii_ipcc_dp:buff_ipcc_data_all0_45_0 , sii_ipcc_dp:buff_ipcc_data_all1_45_0 , sii_ipcc_dp:buff_ipcc_data_all2_45_0 , sii_ipcc_dp:buff_ipcc_data_all3_45_0 
 sii_ipcc_dpbuff_macro__minbuff_1__stack_8r__width_8
File:sii_ipcc_dp.v
Instantiates:buff:d0_0 
Instantiated by:sii_ipcc_dp:buf_sii_mb0_wdata 
 sii_ipcc_dpbuff_macro__minbuff_1__width_64
File:sii_ipcc_dp.v
Instantiates:buff:d0_0 
Instantiated by:sii_ipcc_dp:buf_curhdr_63_0 
 sii_ipcc_dpbuff_macro__minbuff_1__width_8
File:sii_ipcc_dp.v
Instantiates:buff:d0_0 
Instantiated by:sii_ipcc_dp:buf_curhdr_72_64 
 sii_ipcc_dpinv_macro__left_0__stack_4r__width_4
File:sii_ipcc_dp.v
Instantiates:inv:d0_0 
Instantiated by:sii_ipcc_dp:inv_gnt0_r_m 
 sii_ipcc_dpinv_macro__stack_2r__width_2
File:sii_ipcc_dp.v
Instantiates:inv:d0_0 
Instantiated by:sii_ipcc_dp:inv_hdr_data_sel_curhdr58 
 sii_ipcc_dpinv_macro__stack_72r__width_72
File:sii_ipcc_dp.v
Instantiates:inv:d0_0 
Instantiated by:sii_ipcc_dp:inv_curhdr 
 sii_ipcc_dpmsffi_macro__stack_72c__width_72
File:sii_ipcc_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , msffi_dp:d0_0 
Instantiated by:sii_ipcc_dp:ff_curhdri 
 sii_ipcc_dpmsff_macro__stack_14c__width_14
File:sii_ipcc_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sii_ipcc_dp:ff_newbe_par , sii_ipcc_dp:ff_newbe_par_rr , sii_ipcc_dp:ff_ipcc_ecc 
 sii_ipcc_dpmsff_macro__stack_18c__width_18
File:sii_ipcc_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sii_ipcc_dp:ff_newbe 
 sii_ipcc_dpmsff_macro__stack_64c__width_64
File:sii_ipcc_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sii_ipcc_dp:ff_newdata 
 sii_ipcc_dpmsff_macro__stack_72c__width_72
File:sii_ipcc_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sii_ipcc_dp:ff_ipcc_data_out 
 sii_ipcc_dpmsff_macro__stack_8c__width_8
File:sii_ipcc_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sii_ipcc_dp:ff_mb0_wdata 
 sii_ipcc_dpmux_macro__mux_pgdec__ports_4__stack_18c__width_18
File:sii_ipcc_dp.v
Instantiates:cl_dp1_pdec4_8x:c0_0 , mux4:d0_0 
Instantiated by:sii_ipcc_dp:mux_newbe 
 sii_ipcc_dpmux_macro__mux_pgdec__ports_8__stack_14c__width_14
File:sii_ipcc_dp.v
Instantiates:cl_dp1_pdec8_8x:c0_0 , mux8:d0_0 
Instantiated by:sii_ipcc_dp:mux_newbe_par1 
 sii_ipcc_dpmux_macro__mux_pgdec__ports_8__stack_64c__width_64
File:sii_ipcc_dp.v
Instantiates:cl_dp1_pdec8_8x:c0_0 , mux8:d0_0 
Instantiated by:sii_ipcc_dp:mux_newdata_tmp 
 sii_ipcc_dpmux_macro__mux_pgnpe__ports_3__stack_64c__width_64
File:sii_ipcc_dp.v
Instantiates:cl_dp1_muxbuff3_8x:c0_0 , mux3:d0_0 
Instantiated by:sii_ipcc_dp:mux_ipcc_data_out_63_0 
 sii_ipcc_dpmux_macro__mux_pgnpe__ports_5__stack_72c__width_72
File:sii_ipcc_dp.v
Instantiates:cl_dp1_muxbuff5_8x:c0_0 , mux5:d0_0 
Instantiated by:sii_ipcc_dp:mux_curhdr 
 sii_ipcc_dpmux_macro__mux_pgpe__ports_2__stack_14c__width_14
File:sii_ipcc_dp.v
Instantiates:cl_dp1_penc2_8x:c0_0 , mux2e:d0_0 
Instantiated by:sii_ipcc_dp:mux_ipcc_ecc , sii_ipcc_dp:mux_newbe_par 
 sii_ipcc_dpmux_macro__mux_pgpe__ports_2__stack_20c__width_20
File:sii_ipcc_dp.v
Instantiates:cl_dp1_penc2_8x:c0_0 , mux2e:d0_0 
Instantiated by:sii_ipcc_dp:mux_ipcc_data_81_64 
 sii_ipcc_dpmux_macro__mux_pgpe__ports_2__stack_64c__width_64
File:sii_ipcc_dp.v
Instantiates:cl_dp1_penc2_8x:c0_0 , mux2e:d0_0 
Instantiated by:sii_ipcc_dp:mux_ipcc_data_63_0 , sii_ipcc_dp:mux_newdata 
 sii_ipcc_dpmux_macro__mux_pgpe__ports_2__stack_8c__width_8
File:sii_ipcc_dp.v
Instantiates:cl_dp1_penc2_8x:c0_0 , mux2e:d0_0 
Instantiated by:sii_ipcc_dp:mux_ipcc_data_out_71_64 
 sii_ipcc_dpnor_macro__left_0__ports_3__stack_2r__width_1
File:sii_ipcc_dp.v
Instantiates:nor3:d0_0 
Instantiated by:sii_ipcc_dp:nor_gnt0_2 
 sii_ipcc_dpxor_macro__ports_2__stack_10r__width_9
File:sii_ipcc_dp.v
Instantiates:xor2:d0_0 
Instantiated by:sii_ipcc_dp:xor_ecch_0_l1 , sii_ipcc_dp:xor_ecch_1_l1 , sii_ipcc_dp:xor_ecch_2_l1 , sii_ipcc_dp:xor_ecch_6_l1 , sii_ipcc_dp:xor_eccl_0_l1 , sii_ipcc_dp:xor_eccl_1_l1 , sii_ipcc_dp:xor_eccl_2_l1 , sii_ipcc_dp:xor_eccl_6_l1 
 sii_ipcc_dpxor_macro__ports_2__stack_2r__width_1
File:sii_ipcc_dp.v
Instantiates:xor2:d0_0 
Instantiated by:sii_ipcc_dp:xor_ecch_3_l4 , sii_ipcc_dp:xor_ecch_4_l4 , sii_ipcc_dp:xor_eccl_3_l4 , sii_ipcc_dp:xor_eccl_4_l4 
 sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2
File:sii_ipcc_dp.v
Instantiates:xor2:d0_0 
Instantiated by:sii_ipcc_dp:xor_ecch_0_l3 , sii_ipcc_dp:xor_ecch_1_l3 , sii_ipcc_dp:xor_ecch_2_l3 , sii_ipcc_dp:xor_ecch_3_l3 , sii_ipcc_dp:xor_ecch_4_l3 , sii_ipcc_dp:xor_ecch_6_l3 , sii_ipcc_dp:xor_eccl_0_l3 , sii_ipcc_dp:xor_eccl_2_l3 , sii_ipcc_dp:xor_eccl_3_l3 , sii_ipcc_dp:xor_eccl_4_l3 , sii_ipcc_dp:xor_eccl_6_l3 
 sii_ipcc_dpxor_macro__ports_2__stack_4r__width_2
File:sii_ipcc_dp.v
Instantiates:xor2:d0_0 
Instantiated by:sii_ipcc_dp:xor_eccl_1_l3 
 sii_ipcc_dpxor_macro__ports_2__stack_4r__width_3
File:sii_ipcc_dp.v
Instantiates:xor2:d0_0 
Instantiated by:sii_ipcc_dp:xor_ecch_5_l1 , sii_ipcc_dp:xor_eccl_5_l1 
 sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4
File:sii_ipcc_dp.v
Instantiates:xor2:d0_0 
Instantiated by:sii_ipcc_dp:xor_ecc , sii_ipcc_dp:xor_ecch_0_l2 , sii_ipcc_dp:xor_ecch_1_l2 , sii_ipcc_dp:xor_ecch_2_l2 , sii_ipcc_dp:xor_ecch_3_l2 , sii_ipcc_dp:xor_ecch_4_l2 , sii_ipcc_dp:xor_ecch_6_l2 , sii_ipcc_dp:xor_eccl_0_l2 , sii_ipcc_dp:xor_eccl_2_l2 , sii_ipcc_dp:xor_eccl_3_l2 , sii_ipcc_dp:xor_eccl_4_l2 , sii_ipcc_dp:xor_eccl_6_l2 
 sii_ipcc_dpxor_macro__ports_2__stack_8r__width_4
File:sii_ipcc_dp.v
Instantiates:xor2:d0_0 
Instantiated by:sii_ipcc_dp:xor_eccl_1_l2 
 sii_ipcc_dpxor_macro__ports_2__stack_8r__width_7
File:sii_ipcc_dp.v
Instantiates:xor2:d0_0 
Instantiated by:sii_ipcc_dp:xor_ecch_3_l1 , sii_ipcc_dp:xor_ecch_4_l1 , sii_ipcc_dp:xor_eccl_3_l1 , sii_ipcc_dp:xor_eccl_4_l1 
 sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1
File:sii_ipcc_dp.v
Instantiates:xor3:d0_0 
Instantiated by:sii_ipcc_dp:xor_ecch_0_l4 , sii_ipcc_dp:xor_ecch_1_l4 , sii_ipcc_dp:xor_ecch_2_l4 , sii_ipcc_dp:xor_ecch_5_l4 , sii_ipcc_dp:xor_ecch_6_l4 , sii_ipcc_dp:xor_eccl_0_l4 , sii_ipcc_dp:xor_eccl_1_l4 , sii_ipcc_dp:xor_eccl_2_l4 , sii_ipcc_dp:xor_eccl_5_l4 , sii_ipcc_dp:xor_eccl_6_l4 
 sii_ipcs_ctl
File:sii_ipcs_ctl.v
Instantiates:sii_ipcs_ctll1clkhdr_ctl_macro:clkgen , sii_ipcs_ctlspare_ctl_macro__num_20:spares , sii_ipcs_ctlmsff_ctl_macro__width_7:reg_cstate , sii_ipcs_ctlmsff_ctl_macro__width_5:reg_last_or_wr , sii_ipcs_ctlmsff_ctl_macro__width_5:reg_last_by_wr , sii_ipcs_ctlmsff_ctl_macro__width_4:reg_dmu_or_ptr , sii_ipcs_ctlmsff_ctl_macro__width_4:reg_dmu_by_ptr , sii_ipcs_ctlmsff_ctl_macro__width_5:reg_ipdohq_wr_addr , sii_ipcs_ctlmsff_ctl_macro__width_5:reg_ipdbhq_wr_addr , sii_ipcs_ctlmsff_ctl_macro__width_6:reg_ipdodq_wr_addr , sii_ipcs_ctlmsff_ctl_macro__width_6:reg_ipdbdq_wr_addr , sii_ipcs_ctlmsff_ctl_macro__width_128:reg_dmu_sii_hdr , sii_ipcs_ctlmsff_ctl_macro__width_1:reg_datareq16 , sii_ipcs_ctlmsff_ctl_macro__width_1:reg_reqbypass , sii_ipcs_ctlmsff_ctl_macro__width_1:reg_add_or , sii_ipcs_ctlmsff_ctl_macro__width_1:reg_add_by , sii_ipcs_ctlmsff_ctl_macro__width_4:reg_dmu_wrack_tag , sii_ipcs_ctlmsff_ctl_macro__width_1:reg_dmu_wrack_parity , sii_ipcs_ctlmsff_ctl_macro__width_1:reg_ipcc_ipcs_wrack , sii_ipcs_ctlmsff_ctl_macro__width_1:sync_ff_wrack1 , sii_ipcs_ctlmsff_ctl_macro__width_1:sync_ff_wrack2 , sii_ipcs_ctlmsff_ctl_macro__width_1:reg_ipcc_ipcs_or_dq , sii_ipcs_ctlmsff_ctl_macro__width_1:reg_ipcc_ipcs_by_dq , sii_ipcs_ctlmsff_ctl_macro__width_4:sync_ff_or_ptr2 , sii_ipcs_ctlmsff_ctl_macro__width_4:sync_ff_by_ptr1 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_by_cam0 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_by_cam1 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_by_cam2 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_by_cam3 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_by_cam4 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_by_cam5 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_by_cam6 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_by_cam7 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_by_cam8 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_by_cam9 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_by_cam10 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_by_cam11 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_by_cam12 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_by_cam13 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_by_cam14 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_by_cam15 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_or_cam0 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_or_cam1 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_or_cam2 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_or_cam3 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_or_cam4 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_or_cam5 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_or_cam6 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_or_cam7 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_or_cam8 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_or_cam9 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_or_cam10 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_or_cam11 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_or_cam12 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_or_cam13 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_or_cam14 , sii_ipcs_ctlmsff_ctl_macro__width_41:reg_or_cam15 
Instantiated by:sii:ipcs0 , sii:ipcs1 
 sii_ipcs_ctll1clkhdr_ctl_macro
File:sii_ipcs_ctl.v
Instantiates:cl_sc1_l1hdr_8x:c_0 
Instantiated by:sii_ipcs_ctl:clkgen 
 sii_ipcs_ctlmsff_ctl_macro__width_1
File:sii_ipcs_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcs_ctl:reg_datareq16 , sii_ipcs_ctl:reg_reqbypass , sii_ipcs_ctl:reg_add_or , sii_ipcs_ctl:reg_add_by , sii_ipcs_ctl:reg_dmu_wrack_parity , sii_ipcs_ctl:reg_ipcc_ipcs_wrack , sii_ipcs_ctl:sync_ff_wrack1 , sii_ipcs_ctl:sync_ff_wrack2 , sii_ipcs_ctl:reg_ipcc_ipcs_or_dq , sii_ipcs_ctl:reg_ipcc_ipcs_by_dq 
 sii_ipcs_ctlmsff_ctl_macro__width_128
File:sii_ipcs_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcs_ctl:reg_dmu_sii_hdr 
 sii_ipcs_ctlmsff_ctl_macro__width_4
File:sii_ipcs_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcs_ctl:reg_dmu_or_ptr , sii_ipcs_ctl:reg_dmu_by_ptr , sii_ipcs_ctl:reg_dmu_wrack_tag , sii_ipcs_ctl:sync_ff_or_ptr2 , sii_ipcs_ctl:sync_ff_by_ptr1 
 sii_ipcs_ctlmsff_ctl_macro__width_41
File:sii_ipcs_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcs_ctl:reg_by_cam0 , sii_ipcs_ctl:reg_by_cam1 , sii_ipcs_ctl:reg_by_cam2 , sii_ipcs_ctl:reg_by_cam3 , sii_ipcs_ctl:reg_by_cam4 , sii_ipcs_ctl:reg_by_cam5 , sii_ipcs_ctl:reg_by_cam6 , sii_ipcs_ctl:reg_by_cam7 , sii_ipcs_ctl:reg_by_cam8 , sii_ipcs_ctl:reg_by_cam9 , sii_ipcs_ctl:reg_by_cam10 , sii_ipcs_ctl:reg_by_cam11 , sii_ipcs_ctl:reg_by_cam12 , sii_ipcs_ctl:reg_by_cam13 , sii_ipcs_ctl:reg_by_cam14 , sii_ipcs_ctl:reg_by_cam15 , sii_ipcs_ctl:reg_or_cam0 , sii_ipcs_ctl:reg_or_cam1 , sii_ipcs_ctl:reg_or_cam2 , sii_ipcs_ctl:reg_or_cam3 , sii_ipcs_ctl:reg_or_cam4 , sii_ipcs_ctl:reg_or_cam5 , sii_ipcs_ctl:reg_or_cam6 , sii_ipcs_ctl:reg_or_cam7 , sii_ipcs_ctl:reg_or_cam8 , sii_ipcs_ctl:reg_or_cam9 , sii_ipcs_ctl:reg_or_cam10 , sii_ipcs_ctl:reg_or_cam11 , sii_ipcs_ctl:reg_or_cam12 , sii_ipcs_ctl:reg_or_cam13 , sii_ipcs_ctl:reg_or_cam14 , sii_ipcs_ctl:reg_or_cam15 
 sii_ipcs_ctlmsff_ctl_macro__width_5
File:sii_ipcs_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcs_ctl:reg_last_or_wr , sii_ipcs_ctl:reg_last_by_wr , sii_ipcs_ctl:reg_ipdohq_wr_addr , sii_ipcs_ctl:reg_ipdbhq_wr_addr 
 sii_ipcs_ctlmsff_ctl_macro__width_6
File:sii_ipcs_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcs_ctl:reg_ipdodq_wr_addr , sii_ipcs_ctl:reg_ipdbdq_wr_addr 
 sii_ipcs_ctlmsff_ctl_macro__width_7
File:sii_ipcs_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_ipcs_ctl:reg_cstate 
 sii_ipcs_ctlspare_ctl_macro__num_20
File:sii_ipcs_ctl.v
Instantiates:cl_sc1_msff_8x:spare0_flop , cl_u1_buf_32x:spare0_buf_32x , cl_u1_nand3_8x:spare0_nand3_8x , cl_u1_inv_8x:spare0_inv_8x , cl_u1_aoi22_4x:spare0_aoi22_4x , cl_u1_buf_8x:spare0_buf_8x , cl_u1_oai22_4x:spare0_oai22_4x , cl_u1_inv_16x:spare0_inv_16x , cl_u1_nand2_16x:spare0_nand2_16x , cl_u1_nor3_4x:spare0_nor3_4x , cl_u1_nand2_8x:spare0_nand2_8x , cl_u1_buf_16x:spare0_buf_16x , cl_u1_nor2_16x:spare0_nor2_16x , cl_u1_inv_32x:spare0_inv_32x , cl_sc1_msff_8x:spare1_flop , cl_u1_buf_32x:spare1_buf_32x , cl_u1_nand3_8x:spare1_nand3_8x , cl_u1_inv_8x:spare1_inv_8x , cl_u1_aoi22_4x:spare1_aoi22_4x , cl_u1_buf_8x:spare1_buf_8x , cl_u1_oai22_4x:spare1_oai22_4x , cl_u1_inv_16x:spare1_inv_16x , cl_u1_nand2_16x:spare1_nand2_16x , cl_u1_nor3_4x:spare1_nor3_4x , cl_u1_nand2_8x:spare1_nand2_8x , cl_u1_buf_16x:spare1_buf_16x , cl_u1_nor2_16x:spare1_nor2_16x , cl_u1_inv_32x:spare1_inv_32x , cl_sc1_msff_8x:spare2_flop , cl_u1_buf_32x:spare2_buf_32x , cl_u1_nand3_8x:spare2_nand3_8x , cl_u1_inv_8x:spare2_inv_8x , cl_u1_aoi22_4x:spare2_aoi22_4x , cl_u1_buf_8x:spare2_buf_8x , cl_u1_oai22_4x:spare2_oai22_4x , cl_u1_inv_16x:spare2_inv_16x , cl_u1_nand2_16x:spare2_nand2_16x , cl_u1_nor3_4x:spare2_nor3_4x , cl_u1_nand2_8x:spare2_nand2_8x , cl_u1_buf_16x:spare2_buf_16x , cl_u1_nor2_16x:spare2_nor2_16x , cl_u1_inv_32x:spare2_inv_32x , cl_sc1_msff_8x:spare3_flop , cl_u1_buf_32x:spare3_buf_32x , cl_u1_nand3_8x:spare3_nand3_8x , cl_u1_inv_8x:spare3_inv_8x , cl_u1_aoi22_4x:spare3_aoi22_4x , cl_u1_buf_8x:spare3_buf_8x , cl_u1_oai22_4x:spare3_oai22_4x , cl_u1_inv_16x:spare3_inv_16x , cl_u1_nand2_16x:spare3_nand2_16x , cl_u1_nor3_4x:spare3_nor3_4x , cl_u1_nand2_8x:spare3_nand2_8x , cl_u1_buf_16x:spare3_buf_16x , cl_u1_nor2_16x:spare3_nor2_16x , cl_u1_inv_32x:spare3_inv_32x , cl_sc1_msff_8x:spare4_flop , cl_u1_buf_32x:spare4_buf_32x , cl_u1_nand3_8x:spare4_nand3_8x , cl_u1_inv_8x:spare4_inv_8x , cl_u1_aoi22_4x:spare4_aoi22_4x , cl_u1_buf_8x:spare4_buf_8x , cl_u1_oai22_4x:spare4_oai22_4x , cl_u1_inv_16x:spare4_inv_16x , cl_u1_nand2_16x:spare4_nand2_16x , cl_u1_nor3_4x:spare4_nor3_4x , cl_u1_nand2_8x:spare4_nand2_8x , cl_u1_buf_16x:spare4_buf_16x , cl_u1_nor2_16x:spare4_nor2_16x , cl_u1_inv_32x:spare4_inv_32x , cl_sc1_msff_8x:spare5_flop , cl_u1_buf_32x:spare5_buf_32x , cl_u1_nand3_8x:spare5_nand3_8x , cl_u1_inv_8x:spare5_inv_8x , cl_u1_aoi22_4x:spare5_aoi22_4x , cl_u1_buf_8x:spare5_buf_8x , cl_u1_oai22_4x:spare5_oai22_4x , cl_u1_inv_16x:spare5_inv_16x , cl_u1_nand2_16x:spare5_nand2_16x , cl_u1_nor3_4x:spare5_nor3_4x , cl_u1_nand2_8x:spare5_nand2_8x , cl_u1_buf_16x:spare5_buf_16x , cl_u1_nor2_16x:spare5_nor2_16x , cl_u1_inv_32x:spare5_inv_32x , cl_sc1_msff_8x:spare6_flop , cl_u1_buf_32x:spare6_buf_32x , cl_u1_nand3_8x:spare6_nand3_8x , cl_u1_inv_8x:spare6_inv_8x , cl_u1_aoi22_4x:spare6_aoi22_4x , cl_u1_buf_8x:spare6_buf_8x , cl_u1_oai22_4x:spare6_oai22_4x , cl_u1_inv_16x:spare6_inv_16x , cl_u1_nand2_16x:spare6_nand2_16x , cl_u1_nor3_4x:spare6_nor3_4x , cl_u1_nand2_8x:spare6_nand2_8x , cl_u1_buf_16x:spare6_buf_16x , cl_u1_nor2_16x:spare6_nor2_16x , cl_u1_inv_32x:spare6_inv_32x , cl_sc1_msff_8x:spare7_flop , cl_u1_buf_32x:spare7_buf_32x , cl_u1_nand3_8x:spare7_nand3_8x , cl_u1_inv_8x:spare7_inv_8x , cl_u1_aoi22_4x:spare7_aoi22_4x , cl_u1_buf_8x:spare7_buf_8x , cl_u1_oai22_4x:spare7_oai22_4x , cl_u1_inv_16x:spare7_inv_16x , cl_u1_nand2_16x:spare7_nand2_16x , cl_u1_nor3_4x:spare7_nor3_4x , cl_u1_nand2_8x:spare7_nand2_8x , cl_u1_buf_16x:spare7_buf_16x , cl_u1_nor2_16x:spare7_nor2_16x , cl_u1_inv_32x:spare7_inv_32x , cl_sc1_msff_8x:spare8_flop , cl_u1_buf_32x:spare8_buf_32x , cl_u1_nand3_8x:spare8_nand3_8x , cl_u1_inv_8x:spare8_inv_8x , cl_u1_aoi22_4x:spare8_aoi22_4x , cl_u1_buf_8x:spare8_buf_8x , cl_u1_oai22_4x:spare8_oai22_4x , cl_u1_inv_16x:spare8_inv_16x , cl_u1_nand2_16x:spare8_nand2_16x , cl_u1_nor3_4x:spare8_nor3_4x , cl_u1_nand2_8x:spare8_nand2_8x , cl_u1_buf_16x:spare8_buf_16x , cl_u1_nor2_16x:spare8_nor2_16x , cl_u1_inv_32x:spare8_inv_32x , cl_sc1_msff_8x:spare9_flop , cl_u1_buf_32x:spare9_buf_32x , cl_u1_nand3_8x:spare9_nand3_8x , cl_u1_inv_8x:spare9_inv_8x , cl_u1_aoi22_4x:spare9_aoi22_4x , cl_u1_buf_8x:spare9_buf_8x , cl_u1_oai22_4x:spare9_oai22_4x , cl_u1_inv_16x:spare9_inv_16x , cl_u1_nand2_16x:spare9_nand2_16x , cl_u1_nor3_4x:spare9_nor3_4x , cl_u1_nand2_8x:spare9_nand2_8x , cl_u1_buf_16x:spare9_buf_16x , cl_u1_nor2_16x:spare9_nor2_16x , cl_u1_inv_32x:spare9_inv_32x , cl_sc1_msff_8x:spare10_flop , cl_u1_buf_32x:spare10_buf_32x , cl_u1_nand3_8x:spare10_nand3_8x , cl_u1_inv_8x:spare10_inv_8x , cl_u1_aoi22_4x:spare10_aoi22_4x , cl_u1_buf_8x:spare10_buf_8x , cl_u1_oai22_4x:spare10_oai22_4x , cl_u1_inv_16x:spare10_inv_16x , cl_u1_nand2_16x:spare10_nand2_16x , cl_u1_nor3_4x:spare10_nor3_4x , cl_u1_nand2_8x:spare10_nand2_8x , cl_u1_buf_16x:spare10_buf_16x , cl_u1_nor2_16x:spare10_nor2_16x , cl_u1_inv_32x:spare10_inv_32x , cl_sc1_msff_8x:spare11_flop , cl_u1_buf_32x:spare11_buf_32x , cl_u1_nand3_8x:spare11_nand3_8x , cl_u1_inv_8x:spare11_inv_8x , cl_u1_aoi22_4x:spare11_aoi22_4x , cl_u1_buf_8x:spare11_buf_8x , cl_u1_oai22_4x:spare11_oai22_4x , cl_u1_inv_16x:spare11_inv_16x , cl_u1_nand2_16x:spare11_nand2_16x , cl_u1_nor3_4x:spare11_nor3_4x , cl_u1_nand2_8x:spare11_nand2_8x , cl_u1_buf_16x:spare11_buf_16x , cl_u1_nor2_16x:spare11_nor2_16x , cl_u1_inv_32x:spare11_inv_32x , cl_sc1_msff_8x:spare12_flop , cl_u1_buf_32x:spare12_buf_32x , cl_u1_nand3_8x:spare12_nand3_8x , cl_u1_inv_8x:spare12_inv_8x , cl_u1_aoi22_4x:spare12_aoi22_4x , cl_u1_buf_8x:spare12_buf_8x , cl_u1_oai22_4x:spare12_oai22_4x , cl_u1_inv_16x:spare12_inv_16x , cl_u1_nand2_16x:spare12_nand2_16x , cl_u1_nor3_4x:spare12_nor3_4x , cl_u1_nand2_8x:spare12_nand2_8x , cl_u1_buf_16x:spare12_buf_16x , cl_u1_nor2_16x:spare12_nor2_16x , cl_u1_inv_32x:spare12_inv_32x , cl_sc1_msff_8x:spare13_flop , cl_u1_buf_32x:spare13_buf_32x , cl_u1_nand3_8x:spare13_nand3_8x , cl_u1_inv_8x:spare13_inv_8x , cl_u1_aoi22_4x:spare13_aoi22_4x , cl_u1_buf_8x:spare13_buf_8x , cl_u1_oai22_4x:spare13_oai22_4x , cl_u1_inv_16x:spare13_inv_16x , cl_u1_nand2_16x:spare13_nand2_16x , cl_u1_nor3_4x:spare13_nor3_4x , cl_u1_nand2_8x:spare13_nand2_8x , cl_u1_buf_16x:spare13_buf_16x , cl_u1_nor2_16x:spare13_nor2_16x , cl_u1_inv_32x:spare13_inv_32x , cl_sc1_msff_8x:spare14_flop , cl_u1_buf_32x:spare14_buf_32x , cl_u1_nand3_8x:spare14_nand3_8x , cl_u1_inv_8x:spare14_inv_8x , cl_u1_aoi22_4x:spare14_aoi22_4x , cl_u1_buf_8x:spare14_buf_8x , cl_u1_oai22_4x:spare14_oai22_4x , cl_u1_inv_16x:spare14_inv_16x , cl_u1_nand2_16x:spare14_nand2_16x , cl_u1_nor3_4x:spare14_nor3_4x , cl_u1_nand2_8x:spare14_nand2_8x , cl_u1_buf_16x:spare14_buf_16x , cl_u1_nor2_16x:spare14_nor2_16x , cl_u1_inv_32x:spare14_inv_32x , cl_sc1_msff_8x:spare15_flop , cl_u1_buf_32x:spare15_buf_32x , cl_u1_nand3_8x:spare15_nand3_8x , cl_u1_inv_8x:spare15_inv_8x , cl_u1_aoi22_4x:spare15_aoi22_4x , cl_u1_buf_8x:spare15_buf_8x , cl_u1_oai22_4x:spare15_oai22_4x , cl_u1_inv_16x:spare15_inv_16x , cl_u1_nand2_16x:spare15_nand2_16x , cl_u1_nor3_4x:spare15_nor3_4x , cl_u1_nand2_8x:spare15_nand2_8x , cl_u1_buf_16x:spare15_buf_16x , cl_u1_nor2_16x:spare15_nor2_16x , cl_u1_inv_32x:spare15_inv_32x , cl_sc1_msff_8x:spare16_flop , cl_u1_buf_32x:spare16_buf_32x , cl_u1_nand3_8x:spare16_nand3_8x , cl_u1_inv_8x:spare16_inv_8x , cl_u1_aoi22_4x:spare16_aoi22_4x , cl_u1_buf_8x:spare16_buf_8x , cl_u1_oai22_4x:spare16_oai22_4x , cl_u1_inv_16x:spare16_inv_16x , cl_u1_nand2_16x:spare16_nand2_16x , cl_u1_nor3_4x:spare16_nor3_4x , cl_u1_nand2_8x:spare16_nand2_8x , cl_u1_buf_16x:spare16_buf_16x , cl_u1_nor2_16x:spare16_nor2_16x , cl_u1_inv_32x:spare16_inv_32x , cl_sc1_msff_8x:spare17_flop , cl_u1_buf_32x:spare17_buf_32x , cl_u1_nand3_8x:spare17_nand3_8x , cl_u1_inv_8x:spare17_inv_8x , cl_u1_aoi22_4x:spare17_aoi22_4x , cl_u1_buf_8x:spare17_buf_8x , cl_u1_oai22_4x:spare17_oai22_4x , cl_u1_inv_16x:spare17_inv_16x , cl_u1_nand2_16x:spare17_nand2_16x , cl_u1_nor3_4x:spare17_nor3_4x , cl_u1_nand2_8x:spare17_nand2_8x , cl_u1_buf_16x:spare17_buf_16x , cl_u1_nor2_16x:spare17_nor2_16x , cl_u1_inv_32x:spare17_inv_32x , cl_sc1_msff_8x:spare18_flop , cl_u1_buf_32x:spare18_buf_32x , cl_u1_nand3_8x:spare18_nand3_8x , cl_u1_inv_8x:spare18_inv_8x , cl_u1_aoi22_4x:spare18_aoi22_4x , cl_u1_buf_8x:spare18_buf_8x , cl_u1_oai22_4x:spare18_oai22_4x , cl_u1_inv_16x:spare18_inv_16x , cl_u1_nand2_16x:spare18_nand2_16x , cl_u1_nor3_4x:spare18_nor3_4x , cl_u1_nand2_8x:spare18_nand2_8x , cl_u1_buf_16x:spare18_buf_16x , cl_u1_nor2_16x:spare18_nor2_16x , cl_u1_inv_32x:spare18_inv_32x , cl_sc1_msff_8x:spare19_flop , cl_u1_buf_32x:spare19_buf_32x , cl_u1_nand3_8x:spare19_nand3_8x , cl_u1_inv_8x:spare19_inv_8x , cl_u1_aoi22_4x:spare19_aoi22_4x , cl_u1_buf_8x:spare19_buf_8x , cl_u1_oai22_4x:spare19_oai22_4x , cl_u1_inv_16x:spare19_inv_16x , cl_u1_nand2_16x:spare19_nand2_16x , cl_u1_nor3_4x:spare19_nor3_4x , cl_u1_nand2_8x:spare19_nand2_8x , cl_u1_buf_16x:spare19_buf_16x , cl_u1_nor2_16x:spare19_nor2_16x , cl_u1_inv_32x:spare19_inv_32x 
Instantiated by:sii_ipcs_ctl:spares 
 sii_mb0_ctl
File:sii_mb0_ctl.v
Instantiates:sii_mb0_ctll1clkhdr_ctl_macro:clkgen , sii_mb0_ctlmsff_ctl_macro__width_8:config_reg , sii_mb0_ctlmsff_ctl_macro__width_8:user_data_reg , sii_mb0_ctlmsff_ctl_macro__width_6:user_start_addr_reg , sii_mb0_ctlmsff_ctl_macro__width_6:user_stop_addr_reg , sii_mb0_ctlmsff_ctl_macro__width_6:user_incr_addr_reg , sii_mb0_ctlmsff_ctl_macro__width_1:run_reg , sii_mb0_ctlmsff_ctl_macro__width_1:user_bisi_wr_reg , sii_mb0_ctlmsff_ctl_macro__width_1:user_bisi_rd_reg , sii_mb0_ctlmsff_ctl_macro__width_1:start_transition_reg , sii_mb0_ctlmsff_ctl_macro__width_1:run1_reg , sii_mb0_ctlmsff_ctl_macro__width_1:run2_reg , sii_mb0_ctlmsff_ctl_macro__width_6:addr_reg , sii_mb0_ctlmsff_ctl_macro__width_8:wdata_reg , sii_mb0_ctlmsff_ctl_macro__width_2:rd_wr_en_reg , sii_mb0_ctlmsff_ctl_macro__width_2:ild_rd_wr_en_reg , sii_mb0_ctlmsff_ctl_macro__width_1:sii_mb0_fail_reg , sii_mb0_ctlmsff_ctl_macro__width_1:sii_mb0_done_reg , sii_mb0_ctlmsff_ctl_macro__width_18:control_reg , sii_mb0_ctlmsff_ctl_macro__width_3:done_counter_reg , sii_mb0_ctlmsff_ctl_macro__width_1:ind_ren_pipe_reg1 , sii_mb0_ctlmsff_ctl_macro__width_1:ind_ren_pipe_reg2 , sii_mb0_ctlmsff_ctl_macro__width_1:ind_ren_pipe_reg3 , sii_mb0_ctlmsff_ctl_macro__width_1:ind_ren_pipe_reg4 , sii_mb0_ctlmsff_ctl_macro__width_1:ind_ren_pipe_reg5 , sii_mb0_ctlmsff_ctl_macro__width_1:ild_ren_pipe_reg1 , sii_mb0_ctlmsff_ctl_macro__width_1:ild_ren_pipe_reg2 , sii_mb0_ctlmsff_ctl_macro__width_1:ild_ren_pipe_reg3 , sii_mb0_ctlmsff_ctl_macro__width_1:ild_ren_pipe_reg4 , sii_mb0_ctlmsff_ctl_macro__width_1:ild_ren_pipe_reg5 , sii_mb0_ctlmsff_ctl_macro__width_2:ild0_fail_reg , sii_mb0_ctlmsff_ctl_macro__width_2:ild1_fail_reg , sii_mb0_ctlmsff_ctl_macro__width_2:ild2_fail_reg , sii_mb0_ctlmsff_ctl_macro__width_2:ild3_fail_reg , sii_mb0_ctlmsff_ctl_macro__width_2:ild4_fail_reg , sii_mb0_ctlmsff_ctl_macro__width_2:ild5_fail_reg , sii_mb0_ctlmsff_ctl_macro__width_2:ild6_fail_reg , sii_mb0_ctlmsff_ctl_macro__width_2:ild7_fail_reg , sii_mb0_ctlmsff_ctl_macro__width_2:ind_fail_reg , sii_mb0_ctlspare_ctl_macro__num_2:spares , sii_mb0_ctlmsff_ctl_macro__width_18:fail_reg 
Instantiated by:sii:mb0 
 sii_mb0_ctll1clkhdr_ctl_macro
File:sii_mb0_ctl.v
Instantiates:cl_sc1_l1hdr_8x:c_0 
Instantiated by:sii_mb0_ctl:clkgen 
 sii_mb0_ctlmsff_ctl_macro__width_1
File:sii_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_mb0_ctl:run_reg , sii_mb0_ctl:user_bisi_wr_reg , sii_mb0_ctl:user_bisi_rd_reg , sii_mb0_ctl:start_transition_reg , sii_mb0_ctl:run1_reg , sii_mb0_ctl:run2_reg , sii_mb0_ctl:sii_mb0_fail_reg , sii_mb0_ctl:sii_mb0_done_reg , sii_mb0_ctl:ind_ren_pipe_reg1 , sii_mb0_ctl:ind_ren_pipe_reg2 , sii_mb0_ctl:ind_ren_pipe_reg3 , sii_mb0_ctl:ind_ren_pipe_reg4 , sii_mb0_ctl:ind_ren_pipe_reg5 , sii_mb0_ctl:ild_ren_pipe_reg1 , sii_mb0_ctl:ild_ren_pipe_reg2 , sii_mb0_ctl:ild_ren_pipe_reg3 , sii_mb0_ctl:ild_ren_pipe_reg4 , sii_mb0_ctl:ild_ren_pipe_reg5 
 sii_mb0_ctlmsff_ctl_macro__width_18
File:sii_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_mb0_ctl:control_reg , sii_mb0_ctl:fail_reg 
 sii_mb0_ctlmsff_ctl_macro__width_2
File:sii_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_mb0_ctl:rd_wr_en_reg , sii_mb0_ctl:ild_rd_wr_en_reg , sii_mb0_ctl:ild0_fail_reg , sii_mb0_ctl:ild1_fail_reg , sii_mb0_ctl:ild2_fail_reg , sii_mb0_ctl:ild3_fail_reg , sii_mb0_ctl:ild4_fail_reg , sii_mb0_ctl:ild5_fail_reg , sii_mb0_ctl:ild6_fail_reg , sii_mb0_ctl:ild7_fail_reg , sii_mb0_ctl:ind_fail_reg 
 sii_mb0_ctlmsff_ctl_macro__width_3
File:sii_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_mb0_ctl:done_counter_reg 
 sii_mb0_ctlmsff_ctl_macro__width_6
File:sii_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_mb0_ctl:user_start_addr_reg , sii_mb0_ctl:user_stop_addr_reg , sii_mb0_ctl:user_incr_addr_reg , sii_mb0_ctl:addr_reg 
 sii_mb0_ctlmsff_ctl_macro__width_8
File:sii_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_mb0_ctl:config_reg , sii_mb0_ctl:user_data_reg , sii_mb0_ctl:wdata_reg 
 sii_mb0_ctlspare_ctl_macro__num_2
File:sii_mb0_ctl.v
Instantiates:cl_sc1_msff_8x:spare0_flop , cl_u1_buf_32x:spare0_buf_32x , cl_u1_nand3_8x:spare0_nand3_8x , cl_u1_inv_8x:spare0_inv_8x , cl_u1_aoi22_4x:spare0_aoi22_4x , cl_u1_buf_8x:spare0_buf_8x , cl_u1_oai22_4x:spare0_oai22_4x , cl_u1_inv_16x:spare0_inv_16x , cl_u1_nand2_16x:spare0_nand2_16x , cl_u1_nor3_4x:spare0_nor3_4x , cl_u1_nand2_8x:spare0_nand2_8x , cl_u1_buf_16x:spare0_buf_16x , cl_u1_nor2_16x:spare0_nor2_16x , cl_u1_inv_32x:spare0_inv_32x , cl_sc1_msff_8x:spare1_flop , cl_u1_buf_32x:spare1_buf_32x , cl_u1_nand3_8x:spare1_nand3_8x , cl_u1_inv_8x:spare1_inv_8x , cl_u1_aoi22_4x:spare1_aoi22_4x , cl_u1_buf_8x:spare1_buf_8x , cl_u1_oai22_4x:spare1_oai22_4x , cl_u1_inv_16x:spare1_inv_16x , cl_u1_nand2_16x:spare1_nand2_16x , cl_u1_nor3_4x:spare1_nor3_4x , cl_u1_nand2_8x:spare1_nand2_8x , cl_u1_buf_16x:spare1_buf_16x , cl_u1_nor2_16x:spare1_nor2_16x , cl_u1_inv_32x:spare1_inv_32x 
Instantiated by:sii_mb0_ctl:spares 
 sii_mb1_ctl
File:sii_mb1_ctl.v
Instantiates:sii_mb1_ctll1clkhdr_ctl_macro:clkgen , sii_mb1_ctlmsff_ctl_macro__width_9:config_reg , sii_mb1_ctlmsff_ctl_macro__width_8:user_data_reg , sii_mb1_ctlmsff_ctl_macro__width_6:user_start_addr_reg , sii_mb1_ctlmsff_ctl_macro__width_6:user_stop_addr_reg , sii_mb1_ctlmsff_ctl_macro__width_6:user_incr_addr_reg , sii_mb1_ctlmsff_ctl_macro__width_3:user_array_sel_reg , sii_mb1_ctlmsff_ctl_macro__width_1:user_cmpsel_reg , sii_mb1_ctlmsff_ctl_macro__width_1:user_bisi_wr_reg , sii_mb1_ctlmsff_ctl_macro__width_1:user_bisi_rd_reg , sii_mb1_ctlmsff_ctl_macro__width_1:start_transition_reg , sii_mb1_ctlmsff_ctl_macro__width_1:run_reg , sii_mb1_ctlmsff_ctl_macro__width_4:counter_reg , sii_mb1_ctlmsff_ctl_macro__width_78:read_data_reg , sii_mb1_ctlmsff_ctl_macro__width_2:ipdodq0_wr_rd_en_reg , sii_mb1_ctlmsff_ctl_macro__width_1:ipdodq0_wr_en_reg , sii_mb1_ctlmsff_ctl_macro__width_2:ipdodq1_wr_rd_en_reg , sii_mb1_ctlmsff_ctl_macro__width_1:ipdodq1_wr_en_reg , sii_mb1_ctlmsff_ctl_macro__width_2:ipdbdq0_wr_rd_en_reg , sii_mb1_ctlmsff_ctl_macro__width_1:ipdbdq0_wr_en_reg , sii_mb1_ctlmsff_ctl_macro__width_2:ipdbdq1_wr_rd_en_reg , sii_mb1_ctlmsff_ctl_macro__width_1:ipdbdq1_wr_en_reg , sii_mb1_ctlmsff_ctl_macro__width_2:ipdohq0_wr_rd_en_reg , sii_mb1_ctlmsff_ctl_macro__width_1:ipdohq0_wr_en_reg , sii_mb1_ctlmsff_ctl_macro__width_2:ipdohq1_wr_rd_en_reg , sii_mb1_ctlmsff_ctl_macro__width_1:ipdohq1_wr_en_reg , sii_mb1_ctlmsff_ctl_macro__width_2:ipdbhq0_wr_rd_en_reg , sii_mb1_ctlmsff_ctl_macro__width_1:ipdbhq0_wr_en_reg , sii_mb1_ctlmsff_ctl_macro__width_2:ipdbhq1_wr_rd_en_reg , sii_mb1_ctlmsff_ctl_macro__width_1:ipdbhq1_wr_en_reg , sii_mb1_ctlmsff_ctl_macro__width_6:sel_reg , sii_mb1_ctlmsff_ctl_macro__width_6:addr_reg , sii_mb1_ctlmsff_ctl_macro__width_6:wr_addr_reg , sii_mb1_ctlmsff_ctl_macro__width_8:wdata_reg , sii_mb1_ctlmsff_ctl_macro__width_8:wdata_reg2 , sii_mb1_ctlmsff_ctl_macro__width_1:done_reg , sii_mb1_ctlmsff_ctl_macro__width_1:mbist_fail_reg , sii_mb1_ctlmsff_ctl_macro__width_22:control_reg , sii_mb1_ctlmsff_ctl_macro__width_3:done_counter_reg , sii_mb1_ctlmsff_ctl_macro__width_8:data_pipe_reg1 , sii_mb1_ctlmsff_ctl_macro__width_8:data_pipe_reg2 , sii_mb1_ctlmsff_ctl_macro__width_8:data_pipe_reg3 , sii_mb1_ctlmsff_ctl_macro__width_8:data_pipe_reg4 , sii_mb1_ctlmsff_ctl_macro__width_8:data_pipe_reg5 , sii_mb1_ctlmsff_ctl_macro__width_1:ren_pipe_reg1 , sii_mb1_ctlmsff_ctl_macro__width_1:ren_pipe_reg2 , sii_mb1_ctlmsff_ctl_macro__width_1:ren_pipe_reg3 , sii_mb1_ctlmsff_ctl_macro__width_1:ren_pipe_reg4 , sii_mb1_ctlmsff_ctl_macro__width_1:ren_pipe_reg5 , sii_mb1_ctlmsff_ctl_macro__width_1:ren_pipe_reg6 , sii_mb1_ctlmsff_ctl_macro__width_1:ren_pipe_reg7 , sii_mb1_ctlmsff_ctl_macro__width_1:hdr_sel_reg , sii_mb1_ctlmsff_ctl_macro__width_1:hdr_sel_reg2 , sii_mb1_ctlmsff_ctl_macro__width_1:hdr_sel_reg3 , sii_mb1_ctlmsff_ctl_macro__width_1:hdr_sel_reg4 , sii_mb1_ctlmsff_ctl_macro__width_2:encoded_1of4ipd_sel_reg , sii_mb1_ctlmsff_ctl_macro__width_2:encoded_1of4ipd_sel_reg2 , sii_mb1_ctlmsff_ctl_macro__width_2:encoded_1of4ipd_sel_reg3 , sii_mb1_ctlmsff_ctl_macro__width_1:ipd_data_hibits_sel_reg , sii_mb1_ctlmsff_ctl_macro__width_1:ipd_data_hibits_sel_reg2 , sii_mb1_ctlmsff_ctl_macro__width_1:ipd_data_hibits_sel_reg3 , sii_mb1_ctlmsff_ctl_macro__width_6:sel_pipe_reg1 , sii_mb1_ctlmsff_ctl_macro__width_6:sel_pipe_reg2 , sii_mb1_ctlmsff_ctl_macro__width_1:sel_pipe_reg3 , sii_mb1_ctlspare_ctl_macro__num_3:spares , sii_mb1_ctlmsff_ctl_macro__width_8:fail_reg 
Instantiated by:sii:mb1 
 sii_mb1_ctll1clkhdr_ctl_macro
File:sii_mb1_ctl.v
Instantiates:cl_sc1_l1hdr_8x:c_0 
Instantiated by:sii_mb1_ctl:clkgen 
 sii_mb1_ctlmsff_ctl_macro__width_1
File:sii_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_mb1_ctl:user_cmpsel_reg , sii_mb1_ctl:user_bisi_wr_reg , sii_mb1_ctl:user_bisi_rd_reg , sii_mb1_ctl:start_transition_reg , sii_mb1_ctl:run_reg , sii_mb1_ctl:ipdodq0_wr_en_reg , sii_mb1_ctl:ipdodq1_wr_en_reg , sii_mb1_ctl:ipdbdq0_wr_en_reg , sii_mb1_ctl:ipdbdq1_wr_en_reg , sii_mb1_ctl:ipdohq0_wr_en_reg , sii_mb1_ctl:ipdohq1_wr_en_reg , sii_mb1_ctl:ipdbhq0_wr_en_reg , sii_mb1_ctl:ipdbhq1_wr_en_reg , sii_mb1_ctl:done_reg , sii_mb1_ctl:mbist_fail_reg , sii_mb1_ctl:ren_pipe_reg1 , sii_mb1_ctl:ren_pipe_reg2 , sii_mb1_ctl:ren_pipe_reg3 , sii_mb1_ctl:ren_pipe_reg4 , sii_mb1_ctl:ren_pipe_reg5 , sii_mb1_ctl:ren_pipe_reg6 , sii_mb1_ctl:ren_pipe_reg7 , sii_mb1_ctl:hdr_sel_reg , sii_mb1_ctl:hdr_sel_reg2 , sii_mb1_ctl:hdr_sel_reg3 , sii_mb1_ctl:hdr_sel_reg4 , sii_mb1_ctl:ipd_data_hibits_sel_reg , sii_mb1_ctl:ipd_data_hibits_sel_reg2 , sii_mb1_ctl:ipd_data_hibits_sel_reg3 , sii_mb1_ctl:sel_pipe_reg3 
 sii_mb1_ctlmsff_ctl_macro__width_2
File:sii_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_mb1_ctl:ipdodq0_wr_rd_en_reg , sii_mb1_ctl:ipdodq1_wr_rd_en_reg , sii_mb1_ctl:ipdbdq0_wr_rd_en_reg , sii_mb1_ctl:ipdbdq1_wr_rd_en_reg , sii_mb1_ctl:ipdohq0_wr_rd_en_reg , sii_mb1_ctl:ipdohq1_wr_rd_en_reg , sii_mb1_ctl:ipdbhq0_wr_rd_en_reg , sii_mb1_ctl:ipdbhq1_wr_rd_en_reg , sii_mb1_ctl:encoded_1of4ipd_sel_reg , sii_mb1_ctl:encoded_1of4ipd_sel_reg2 , sii_mb1_ctl:encoded_1of4ipd_sel_reg3 
 sii_mb1_ctlmsff_ctl_macro__width_22
File:sii_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_mb1_ctl:control_reg 
 sii_mb1_ctlmsff_ctl_macro__width_3
File:sii_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_mb1_ctl:user_array_sel_reg , sii_mb1_ctl:done_counter_reg 
 sii_mb1_ctlmsff_ctl_macro__width_4
File:sii_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_mb1_ctl:counter_reg 
 sii_mb1_ctlmsff_ctl_macro__width_6
File:sii_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_mb1_ctl:user_start_addr_reg , sii_mb1_ctl:user_stop_addr_reg , sii_mb1_ctl:user_incr_addr_reg , sii_mb1_ctl:sel_reg , sii_mb1_ctl:addr_reg , sii_mb1_ctl:wr_addr_reg , sii_mb1_ctl:sel_pipe_reg1 , sii_mb1_ctl:sel_pipe_reg2 
 sii_mb1_ctlmsff_ctl_macro__width_78
File:sii_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_mb1_ctl:read_data_reg 
 sii_mb1_ctlmsff_ctl_macro__width_8
File:sii_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_mb1_ctl:user_data_reg , sii_mb1_ctl:wdata_reg , sii_mb1_ctl:wdata_reg2 , sii_mb1_ctl:data_pipe_reg1 , sii_mb1_ctl:data_pipe_reg2 , sii_mb1_ctl:data_pipe_reg3 , sii_mb1_ctl:data_pipe_reg4 , sii_mb1_ctl:data_pipe_reg5 , sii_mb1_ctl:fail_reg 
 sii_mb1_ctlmsff_ctl_macro__width_9
File:sii_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sii_mb1_ctl:config_reg 
 sii_mb1_ctlspare_ctl_macro__num_3
File:sii_mb1_ctl.v
Instantiates:cl_sc1_msff_8x:spare0_flop , cl_u1_buf_32x:spare0_buf_32x , cl_u1_nand3_8x:spare0_nand3_8x , cl_u1_inv_8x:spare0_inv_8x , cl_u1_aoi22_4x:spare0_aoi22_4x , cl_u1_buf_8x:spare0_buf_8x , cl_u1_oai22_4x:spare0_oai22_4x , cl_u1_inv_16x:spare0_inv_16x , cl_u1_nand2_16x:spare0_nand2_16x , cl_u1_nor3_4x:spare0_nor3_4x , cl_u1_nand2_8x:spare0_nand2_8x , cl_u1_buf_16x:spare0_buf_16x , cl_u1_nor2_16x:spare0_nor2_16x , cl_u1_inv_32x:spare0_inv_32x , cl_sc1_msff_8x:spare1_flop , cl_u1_buf_32x:spare1_buf_32x , cl_u1_nand3_8x:spare1_nand3_8x , cl_u1_inv_8x:spare1_inv_8x , cl_u1_aoi22_4x:spare1_aoi22_4x , cl_u1_buf_8x:spare1_buf_8x , cl_u1_oai22_4x:spare1_oai22_4x , cl_u1_inv_16x:spare1_inv_16x , cl_u1_nand2_16x:spare1_nand2_16x , cl_u1_nor3_4x:spare1_nor3_4x , cl_u1_nand2_8x:spare1_nand2_8x , cl_u1_buf_16x:spare1_buf_16x , cl_u1_nor2_16x:spare1_nor2_16x , cl_u1_inv_32x:spare1_inv_32x , cl_sc1_msff_8x:spare2_flop , cl_u1_buf_32x:spare2_buf_32x , cl_u1_nand3_8x:spare2_nand3_8x , cl_u1_inv_8x:spare2_inv_8x , cl_u1_aoi22_4x:spare2_aoi22_4x , cl_u1_buf_8x:spare2_buf_8x , cl_u1_oai22_4x:spare2_oai22_4x , cl_u1_inv_16x:spare2_inv_16x , cl_u1_nand2_16x:spare2_nand2_16x , cl_u1_nor3_4x:spare2_nor3_4x , cl_u1_nand2_8x:spare2_nand2_8x , cl_u1_buf_16x:spare2_buf_16x , cl_u1_nor2_16x:spare2_nor2_16x , cl_u1_inv_32x:spare2_inv_32x 
Instantiated by:sii_mb1_ctl:spares 
 sii_stgsio_dp
File:sii_stgsio_dp.v
Instantiates:sii_stgsio_dpmsff_macro__stack_2c__width_2:dff_sio_sii_opcc_ipcc_dmu_deq , sii_stgsio_dpmsff_macro__stack_2c__width_2:dff_sio_sii_opcc_ipcc_niu_deq , sii_stgsio_dpmsff_macro__stack_4c__width_4:dff_sio_sii_opcc_ipcc_dmu_by_cnt , sii_stgsio_dpmsff_macro__stack_4c__width_4:dff_sio_sii_opcc_ipcc_niu_by_cnt , sii_stgsio_dpmsff_macro__stack_8c__width_8:dff_sio_sii_olc_ilc_dequeue 
Instantiated by:sii:stgsio_dp 
 sii_stgsio_dpmsff_macro__stack_2c__width_2
File:sii_stgsio_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sii_stgsio_dp:dff_sio_sii_opcc_ipcc_dmu_deq , sii_stgsio_dp:dff_sio_sii_opcc_ipcc_niu_deq 
 sii_stgsio_dpmsff_macro__stack_4c__width_4
File:sii_stgsio_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sii_stgsio_dp:dff_sio_sii_opcc_ipcc_dmu_by_cnt , sii_stgsio_dp:dff_sio_sii_opcc_ipcc_niu_by_cnt 
 sii_stgsio_dpmsff_macro__stack_8c__width_8
File:sii_stgsio_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sii_stgsio_dp:dff_sio_sii_olc_ilc_dequeue 
 sio
File:sio.v
Instantiates:sio_mb0_ctl:mb0 , sio_mb1_ctl:mb1 , n2_com_dp_32x34_cust:olddq00 , n2_com_dp_32x34_cust:olddq01 , sio_old_dp:old0 , sio_olc_ctl:olc0 , sio_stg1_dp:stg1 , n2_com_dp_32x34_cust:olddq10 , n2_com_dp_32x34_cust:olddq11 , sio_old_dp:old1 , sio_olc_ctl:olc1 , sio_stg1_dp:stg2 , n2_com_dp_32x34_cust:olddq20 , n2_com_dp_32x34_cust:olddq21 , sio_old_dp:old2 , sio_olc_ctl:olc2 , sio_stg1_dp:stg3 , n2_com_dp_32x34_cust:olddq30 , n2_com_dp_32x34_cust:olddq31 , sio_old_dp:old3 , sio_olc_ctl:olc3 , sio_stg1_dp:stg4 , n2_com_dp_32x34_cust:olddq40 , n2_com_dp_32x34_cust:olddq41 , sio_old_dp:old4 , sio_olc_ctl:olc4 , sio_stg2_dp:stg5 , n2_com_dp_32x34_cust:olddq50 , n2_com_dp_32x34_cust:olddq51 , sio_old_dp:old5 , sio_olc_ctl:olc5 , sio_stg2_dp:stg6 , n2_com_dp_32x34_cust:olddq60 , n2_com_dp_32x34_cust:olddq61 , sio_old_dp:old6 , sio_olc_ctl:olc6 , sio_stg2_dp:stg7 , n2_com_dp_32x34_cust:olddq70 , n2_com_dp_32x34_cust:olddq71 , sio_old_dp:old7 , sio_olc_ctl:olc7 , sio_opdc_dp:opdc , n2_com_dp_64x72s_cust:opddq00 , n2_com_dp_64x72s_cust:opddq01 , n2_com_dp_64x72s_cust:opddq10 , n2_com_dp_64x72s_cust:opddq11 , n2_com_dp_16x32s_cust:opdhq0 , n2_com_dp_16x32s_cust:opdhq1 , sio_opds_dp:opds0 , sio_opds_dp:opds1 , sio_opcc_ctl:opcc , sio_opcs_ctl:opcs0 , sio_opcs_ctl:opcs1 , clkgen_sio_cmp:clkgen_cmp , clkgen_sio_io:clkgen_io 
Instantiated by:cpu:sio 
 sio_mb0_ctl
File:sio_mb0_ctl.v
Instantiates:sio_mb0_ctl_l1clkhdr_ctl_macro:clkgen , sio_mb0_ctl_msff_ctl_macro__width_8:config_reg , sio_mb0_ctl_msff_ctl_macro__width_8:user_data_reg , sio_mb0_ctl_msff_ctl_macro__width_5:user_start_addr_reg , sio_mb0_ctl_msff_ctl_macro__width_5:user_stop_addr_reg , sio_mb0_ctl_msff_ctl_macro__width_5:user_incr_addr_reg , sio_mb0_ctl_msff_ctl_macro__width_3:user_array_sel_reg , sio_mb0_ctl_msff_ctl_macro__width_1:user_bisi_wr_reg , sio_mb0_ctl_msff_ctl_macro__width_1:user_bisi_rd_reg , sio_mb0_ctl_msff_ctl_macro__width_1:start_transition_reg , sio_mb0_ctl_msff_ctl_macro__width_1:run_reg , sio_mb0_ctl_msff_ctl_macro__width_1:run1_reg , sio_mb0_ctl_msff_ctl_macro__width_1:run2_reg , sio_mb0_ctl_msff_ctl_macro__width_5:addr_reg , sio_mb0_ctl_msff_ctl_macro__width_8:wdata_reg , sio_mb0_ctl_msff_ctl_macro__width_2:rd_wr_en_reg0 , sio_mb0_ctl_msff_ctl_macro__width_2:rd_wr_en_reg1 , sio_mb0_ctl_msff_ctl_macro__width_2:rd_wr_en_reg2 , sio_mb0_ctl_msff_ctl_macro__width_2:rd_wr_en_reg3 , sio_mb0_ctl_msff_ctl_macro__width_2:rd_wr_en_reg4 , sio_mb0_ctl_msff_ctl_macro__width_2:rd_wr_en_reg5 , sio_mb0_ctl_msff_ctl_macro__width_2:rd_wr_en_reg6 , sio_mb0_ctl_msff_ctl_macro__width_2:rd_wr_en_reg7 , sio_mb0_ctl_msff_ctl_macro__width_1:sio_mb0_fail_reg , sio_mb0_ctl_msff_ctl_macro__width_1:sio_mb0_done_reg , sio_mb0_ctl_msff_ctl_macro__width_68:read_data_pipe_reg , sio_mb0_ctl_msff_ctl_macro__width_20:control_reg , sio_mb0_ctl_msff_ctl_macro__width_3:done_counter_reg , sio_mb0_ctl_msff_ctl_macro__width_8:data_pipe_reg1 , sio_mb0_ctl_msff_ctl_macro__width_8:data_pipe_reg2 , sio_mb0_ctl_msff_ctl_macro__width_8:data_pipe_reg3 , sio_mb0_ctl_msff_ctl_macro__width_8:data_pipe_reg4 , sio_mb0_ctl_msff_ctl_macro__width_1:ren_pipe_reg1 , sio_mb0_ctl_msff_ctl_macro__width_1:ren_pipe_reg2 , sio_mb0_ctl_msff_ctl_macro__width_1:ren_pipe_reg3 , sio_mb0_ctl_msff_ctl_macro__width_1:ren_pipe_reg4 , sio_mb0_ctl_msff_ctl_macro__width_1:ren_pipe_reg5 , sio_mb0_ctl_msff_ctl_macro__width_3:ary_sel_pipe_reg1 , sio_mb0_ctl_msff_ctl_macro__width_3:ary_sel_pipe_reg2 , sio_mb0_ctl_msff_ctl_macro__width_3:ary_sel_pipe_reg3 , sio_mb0_ctl_msff_ctl_macro__width_3:ary_sel_pipe_reg4 , sio_mb0_ctl_msff_ctl_macro__width_3:ary_sel_pipe_reg5 , sio_mb0_ctl_spare_ctl_macro__num_3:spares , sio_mb0_ctl_msff_ctl_macro__width_8:fail_reg 
Instantiated by:sio:mb0 
 sio_mb0_ctl_l1clkhdr_ctl_macro
File:sio_mb0_ctl.v
Instantiates:cl_sc1_l1hdr_8x:c_0 
Instantiated by:sio_mb0_ctl:clkgen 
 sio_mb0_ctl_msff_ctl_macro__width_1
File:sio_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_mb0_ctl:user_bisi_wr_reg , sio_mb0_ctl:user_bisi_rd_reg , sio_mb0_ctl:start_transition_reg , sio_mb0_ctl:run_reg , sio_mb0_ctl:run1_reg , sio_mb0_ctl:run2_reg , sio_mb0_ctl:sio_mb0_fail_reg , sio_mb0_ctl:sio_mb0_done_reg , sio_mb0_ctl:ren_pipe_reg1 , sio_mb0_ctl:ren_pipe_reg2 , sio_mb0_ctl:ren_pipe_reg3 , sio_mb0_ctl:ren_pipe_reg4 , sio_mb0_ctl:ren_pipe_reg5 
 sio_mb0_ctl_msff_ctl_macro__width_2
File:sio_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_mb0_ctl:rd_wr_en_reg0 , sio_mb0_ctl:rd_wr_en_reg1 , sio_mb0_ctl:rd_wr_en_reg2 , sio_mb0_ctl:rd_wr_en_reg3 , sio_mb0_ctl:rd_wr_en_reg4 , sio_mb0_ctl:rd_wr_en_reg5 , sio_mb0_ctl:rd_wr_en_reg6 , sio_mb0_ctl:rd_wr_en_reg7 
 sio_mb0_ctl_msff_ctl_macro__width_20
File:sio_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_mb0_ctl:control_reg 
 sio_mb0_ctl_msff_ctl_macro__width_3
File:sio_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_mb0_ctl:user_array_sel_reg , sio_mb0_ctl:done_counter_reg , sio_mb0_ctl:ary_sel_pipe_reg1 , sio_mb0_ctl:ary_sel_pipe_reg2 , sio_mb0_ctl:ary_sel_pipe_reg3 , sio_mb0_ctl:ary_sel_pipe_reg4 , sio_mb0_ctl:ary_sel_pipe_reg5 
 sio_mb0_ctl_msff_ctl_macro__width_5
File:sio_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_mb0_ctl:user_start_addr_reg , sio_mb0_ctl:user_stop_addr_reg , sio_mb0_ctl:user_incr_addr_reg , sio_mb0_ctl:addr_reg 
 sio_mb0_ctl_msff_ctl_macro__width_68
File:sio_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_mb0_ctl:read_data_pipe_reg 
 sio_mb0_ctl_msff_ctl_macro__width_8
File:sio_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_mb0_ctl:config_reg , sio_mb0_ctl:user_data_reg , sio_mb0_ctl:wdata_reg , sio_mb0_ctl:data_pipe_reg1 , sio_mb0_ctl:data_pipe_reg2 , sio_mb0_ctl:data_pipe_reg3 , sio_mb0_ctl:data_pipe_reg4 , sio_mb0_ctl:fail_reg 
 sio_mb0_ctl_spare_ctl_macro__num_3
File:sio_mb0_ctl.v
Instantiates:cl_sc1_msff_8x:spare0_flop , cl_u1_buf_32x:spare0_buf_32x , cl_u1_nand3_8x:spare0_nand3_8x , cl_u1_inv_8x:spare0_inv_8x , cl_u1_aoi22_4x:spare0_aoi22_4x , cl_u1_buf_8x:spare0_buf_8x , cl_u1_oai22_4x:spare0_oai22_4x , cl_u1_inv_16x:spare0_inv_16x , cl_u1_nand2_16x:spare0_nand2_16x , cl_u1_nor3_4x:spare0_nor3_4x , cl_u1_nand2_8x:spare0_nand2_8x , cl_u1_buf_16x:spare0_buf_16x , cl_u1_nor2_16x:spare0_nor2_16x , cl_u1_inv_32x:spare0_inv_32x , cl_sc1_msff_8x:spare1_flop , cl_u1_buf_32x:spare1_buf_32x , cl_u1_nand3_8x:spare1_nand3_8x , cl_u1_inv_8x:spare1_inv_8x , cl_u1_aoi22_4x:spare1_aoi22_4x , cl_u1_buf_8x:spare1_buf_8x , cl_u1_oai22_4x:spare1_oai22_4x , cl_u1_inv_16x:spare1_inv_16x , cl_u1_nand2_16x:spare1_nand2_16x , cl_u1_nor3_4x:spare1_nor3_4x , cl_u1_nand2_8x:spare1_nand2_8x , cl_u1_buf_16x:spare1_buf_16x , cl_u1_nor2_16x:spare1_nor2_16x , cl_u1_inv_32x:spare1_inv_32x , cl_sc1_msff_8x:spare2_flop , cl_u1_buf_32x:spare2_buf_32x , cl_u1_nand3_8x:spare2_nand3_8x , cl_u1_inv_8x:spare2_inv_8x , cl_u1_aoi22_4x:spare2_aoi22_4x , cl_u1_buf_8x:spare2_buf_8x , cl_u1_oai22_4x:spare2_oai22_4x , cl_u1_inv_16x:spare2_inv_16x , cl_u1_nand2_16x:spare2_nand2_16x , cl_u1_nor3_4x:spare2_nor3_4x , cl_u1_nand2_8x:spare2_nand2_8x , cl_u1_buf_16x:spare2_buf_16x , cl_u1_nor2_16x:spare2_nor2_16x , cl_u1_inv_32x:spare2_inv_32x 
Instantiated by:sio_mb0_ctl:spares 
 sio_mb1_ctl
File:sio_mb1_ctl.v
Instantiates:sio_mb1_ctl_l1clkhdr_ctl_macro:clkgen , sio_mb1_ctl_msff_ctl_macro__width_8:config_reg , sio_mb1_ctl_msff_ctl_macro__width_8:user_data_reg , sio_mb1_ctl_msff_ctl_macro__width_6:user_start_addr_reg , sio_mb1_ctl_msff_ctl_macro__width_6:user_stop_addr_reg , sio_mb1_ctl_msff_ctl_macro__width_6:user_incr_addr_reg , sio_mb1_ctl_msff_ctl_macro__width_3:user_array_sel_reg , sio_mb1_ctl_msff_ctl_macro__width_1:user_bisi_wr_reg , sio_mb1_ctl_msff_ctl_macro__width_1:user_bisi_rd_reg , sio_mb1_ctl_msff_ctl_macro__width_1:start_transition_reg , sio_mb1_ctl_msff_ctl_macro__width_1:run_reg , sio_mb1_ctl_msff_ctl_macro__width_4:counter_reg , sio_mb1_ctl_msff_ctl_macro__width_6:addr_reg , sio_mb1_ctl_msff_ctl_macro__width_8:wdata_reg , sio_mb1_ctl_msff_ctl_macro__width_2:wr_rd_en_reg0 , sio_mb1_ctl_msff_ctl_macro__width_2:wr_rd_en_reg1 , sio_mb1_ctl_msff_ctl_macro__width_2:wr_rd_en_reg2 , sio_mb1_ctl_msff_ctl_macro__width_2:wr_rd_en_reg3 , sio_mb1_ctl_msff_ctl_macro__width_2:wr_rd_en_reg4 , sio_mb1_ctl_msff_ctl_macro__width_2:wr_rd_en_reg5 , sio_mb1_ctl_msff_ctl_macro__width_3:sel_reg , sio_mb1_ctl_msff_ctl_macro__width_1:done_reg , sio_mb1_ctl_msff_ctl_macro__width_1:new_fail_reg , sio_mb1_ctl_msff_ctl_macro__width_21:control_reg , sio_mb1_ctl_msff_ctl_macro__width_3:done_counter_reg , sio_mb1_ctl_msff_ctl_macro__width_8:data_pipe_reg1 , sio_mb1_ctl_msff_ctl_macro__width_8:data_pipe_reg2 , sio_mb1_ctl_msff_ctl_macro__width_8:data_pipe_reg3 , sio_mb1_ctl_msff_ctl_macro__width_1:ren_pipe_reg1 , sio_mb1_ctl_msff_ctl_macro__width_1:ren_pipe_reg2 , sio_mb1_ctl_msff_ctl_macro__width_1:ren_pipe_reg3 , sio_mb1_ctl_msff_ctl_macro__width_1:ren_pipe_reg4 , sio_mb1_ctl_msff_ctl_macro__width_3:opd_sel_reg1 , sio_mb1_ctl_msff_ctl_macro__width_3:opd_sel_reg2 , sio_mb1_ctl_msff_ctl_macro__width_3:opd_sel_reg4 , sio_mb1_ctl_msff_ctl_macro__width_1:opd1or0_sel_reg1 , sio_mb1_ctl_msff_ctl_macro__width_1:opd1or0_sel_reg2 , sio_mb1_ctl_msff_ctl_macro__width_1:opd1or0_sel_reg3 , sio_mb1_ctl_msff_ctl_macro__width_1:opd1or0_sel_reg4 , sio_mb1_ctl_spare_ctl_macro__num_3:spares , sio_mb1_ctl_msff_ctl_macro__width_72:read_data_pipe_reg , sio_mb1_ctl_msff_ctl_macro__width_6:fail_reg 
Instantiated by:sio:mb1 
 sio_mb1_ctl_l1clkhdr_ctl_macro
File:sio_mb1_ctl.v
Instantiates:cl_sc1_l1hdr_8x:c_0 
Instantiated by:sio_mb1_ctl:clkgen 
 sio_mb1_ctl_msff_ctl_macro__width_1
File:sio_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_mb1_ctl:user_bisi_wr_reg , sio_mb1_ctl:user_bisi_rd_reg , sio_mb1_ctl:start_transition_reg , sio_mb1_ctl:run_reg , sio_mb1_ctl:done_reg , sio_mb1_ctl:new_fail_reg , sio_mb1_ctl:ren_pipe_reg1 , sio_mb1_ctl:ren_pipe_reg2 , sio_mb1_ctl:ren_pipe_reg3 , sio_mb1_ctl:ren_pipe_reg4 , sio_mb1_ctl:opd1or0_sel_reg1 , sio_mb1_ctl:opd1or0_sel_reg2 , sio_mb1_ctl:opd1or0_sel_reg3 , sio_mb1_ctl:opd1or0_sel_reg4 
 sio_mb1_ctl_msff_ctl_macro__width_2
File:sio_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_mb1_ctl:wr_rd_en_reg0 , sio_mb1_ctl:wr_rd_en_reg1 , sio_mb1_ctl:wr_rd_en_reg2 , sio_mb1_ctl:wr_rd_en_reg3 , sio_mb1_ctl:wr_rd_en_reg4 , sio_mb1_ctl:wr_rd_en_reg5 
 sio_mb1_ctl_msff_ctl_macro__width_21
File:sio_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_mb1_ctl:control_reg 
 sio_mb1_ctl_msff_ctl_macro__width_3
File:sio_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_mb1_ctl:user_array_sel_reg , sio_mb1_ctl:sel_reg , sio_mb1_ctl:done_counter_reg , sio_mb1_ctl:opd_sel_reg1 , sio_mb1_ctl:opd_sel_reg2 , sio_mb1_ctl:opd_sel_reg4 
 sio_mb1_ctl_msff_ctl_macro__width_4
File:sio_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_mb1_ctl:counter_reg 
 sio_mb1_ctl_msff_ctl_macro__width_6
File:sio_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_mb1_ctl:user_start_addr_reg , sio_mb1_ctl:user_stop_addr_reg , sio_mb1_ctl:user_incr_addr_reg , sio_mb1_ctl:addr_reg , sio_mb1_ctl:fail_reg 
 sio_mb1_ctl_msff_ctl_macro__width_72
File:sio_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_mb1_ctl:read_data_pipe_reg 
 sio_mb1_ctl_msff_ctl_macro__width_8
File:sio_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_mb1_ctl:config_reg , sio_mb1_ctl:user_data_reg , sio_mb1_ctl:wdata_reg , sio_mb1_ctl:data_pipe_reg1 , sio_mb1_ctl:data_pipe_reg2 , sio_mb1_ctl:data_pipe_reg3 
 sio_mb1_ctl_spare_ctl_macro__num_3
File:sio_mb1_ctl.v
Instantiates:cl_sc1_msff_8x:spare0_flop , cl_u1_buf_32x:spare0_buf_32x , cl_u1_nand3_8x:spare0_nand3_8x , cl_u1_inv_8x:spare0_inv_8x , cl_u1_aoi22_4x:spare0_aoi22_4x , cl_u1_buf_8x:spare0_buf_8x , cl_u1_oai22_4x:spare0_oai22_4x , cl_u1_inv_16x:spare0_inv_16x , cl_u1_nand2_16x:spare0_nand2_16x , cl_u1_nor3_4x:spare0_nor3_4x , cl_u1_nand2_8x:spare0_nand2_8x , cl_u1_buf_16x:spare0_buf_16x , cl_u1_nor2_16x:spare0_nor2_16x , cl_u1_inv_32x:spare0_inv_32x , cl_sc1_msff_8x:spare1_flop , cl_u1_buf_32x:spare1_buf_32x , cl_u1_nand3_8x:spare1_nand3_8x , cl_u1_inv_8x:spare1_inv_8x , cl_u1_aoi22_4x:spare1_aoi22_4x , cl_u1_buf_8x:spare1_buf_8x , cl_u1_oai22_4x:spare1_oai22_4x , cl_u1_inv_16x:spare1_inv_16x , cl_u1_nand2_16x:spare1_nand2_16x , cl_u1_nor3_4x:spare1_nor3_4x , cl_u1_nand2_8x:spare1_nand2_8x , cl_u1_buf_16x:spare1_buf_16x , cl_u1_nor2_16x:spare1_nor2_16x , cl_u1_inv_32x:spare1_inv_32x , cl_sc1_msff_8x:spare2_flop , cl_u1_buf_32x:spare2_buf_32x , cl_u1_nand3_8x:spare2_nand3_8x , cl_u1_inv_8x:spare2_inv_8x , cl_u1_aoi22_4x:spare2_aoi22_4x , cl_u1_buf_8x:spare2_buf_8x , cl_u1_oai22_4x:spare2_oai22_4x , cl_u1_inv_16x:spare2_inv_16x , cl_u1_nand2_16x:spare2_nand2_16x , cl_u1_nor3_4x:spare2_nor3_4x , cl_u1_nand2_8x:spare2_nand2_8x , cl_u1_buf_16x:spare2_buf_16x , cl_u1_nor2_16x:spare2_nor2_16x , cl_u1_inv_32x:spare2_inv_32x 
Instantiated by:sio_mb1_ctl:spares 
 sio_olc_ctl
File:sio_olc_ctl.v
Instantiates:sio_olc_ctl_l1clkhdr_ctl_macro:clkgen , cl_sc1_msff_8x:ff_ojc_old_jtagsr_en , cl_u1_buf_32x:spare0_buf_32x , cl_u1_nand3_8x:spare0_nand3_8x , cl_u1_inv_8x:spare0_inv_8x , cl_u1_aoi22_4x:spare0_aoi22_4x , cl_u1_buf_8x:spare0_buf_8x , cl_u1_oai22_4x:spare0_oai22_4x , cl_u1_inv_16x:spare0_inv_16x , cl_u1_nand2_16x:spare0_nand2_16x , cl_u1_nor3_4x:spare0_nor3_4x , cl_u1_nand2_8x:spare0_nand2_8x , cl_u1_buf_16x:spare0_buf_16x , cl_u1_nor2_16x:spare0_nor2_16x , cl_u1_inv_32x:spare0_inv_32x , sio_olc_ctl_msff_ctl_macro__width_4:ff_ojc_cycle_sox , sio_olc_ctl_msff_ctl_macro__width_4:ff_ojc_ack_sox , sio_olc_ctl_msff_ctl_macro__width_6:ff_ojc_shcnt , sio_olc_ctl_msff_ctl_macro__width_1:ff_pass_late_ue , sio_olc_ctl_msff_ctl_macro__width_1:ff_l2b_sio_ue_err , sio_olc_ctl_msff_ctl_macro__width_17:ff_olc_cycle , sio_olc_ctl_msff_ctl_macro__width_3:ff_hq_wr_ptr , sio_olc_ctl_msff_ctl_macro__width_7:ff_pq_wr_ptr , sio_olc_ctl_msff_ctl_macro__width_2:ff_pq_wr_en , sio_olc_ctl_msff_ctl_macro__width_2:ff_ue_en , sio_olc_ctl_msff_ctl_macro__width_3:ff_ue_wr_ptr , sio_olc_ctl_msff_ctl_macro__width_2:ff_slp_cycle , sio_olc_ctl_msff_ctl_macro__width_1:ff_header_now_access_same_entry , sio_olc_ctl_msff_ctl_macro__width_2:ff_payload_readys , sio_olc_ctl_msff_ctl_macro__width_1:ff_ue_rd_ptr_inc , sio_olc_ctl_msff_ctl_macro__width_3:ff_hq_rd_ptr , sio_olc_ctl_msff_ctl_macro__width_1:ff_dequeue , sio_olc_ctl_msff_ctl_macro__width_7:ff_pq_rd_ptr , sio_olc_ctl_msff_ctl_macro__width_2:ff_pq_rd_en , sio_olc_ctl_msff_ctl_macro__width_3:ff_ue_rd_ptr , sio_olc_ctl_msff_ctl_macro__width_1:ff_l2sio_r_bit0 , sio_olc_ctl_msff_ctl_macro__width_1:ff_l2sio_r_bit1 , sio_olc_ctl_msff_ctl_macro__width_1:ff_l2sio_r_bit2 , sio_olc_ctl_msff_ctl_macro__width_1:ff_l2sio_r_bit3 , sio_olc_ctl_msff_ctl_macro__width_1:ff_l2sio_r_bit 
Instantiated by:sio:olc0 , sio:olc1 , sio:olc2 , sio:olc3 , sio:olc4 , sio:olc5 , sio:olc6 , sio:olc7 
 sio_olc_ctl_l1clkhdr_ctl_macro
File:sio_olc_ctl.v
Instantiates:cl_sc1_l1hdr_8x:c_0 
Instantiated by:sio_olc_ctl:clkgen 
 sio_olc_ctl_msff_ctl_macro__width_1
File:sio_olc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_olc_ctl:ff_pass_late_ue , sio_olc_ctl:ff_l2b_sio_ue_err , sio_olc_ctl:ff_header_now_access_same_entry , sio_olc_ctl:ff_ue_rd_ptr_inc , sio_olc_ctl:ff_dequeue , sio_olc_ctl:ff_l2sio_r_bit0 , sio_olc_ctl:ff_l2sio_r_bit1 , sio_olc_ctl:ff_l2sio_r_bit2 , sio_olc_ctl:ff_l2sio_r_bit3 , sio_olc_ctl:ff_l2sio_r_bit 
 sio_olc_ctl_msff_ctl_macro__width_17
File:sio_olc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_olc_ctl:ff_olc_cycle 
 sio_olc_ctl_msff_ctl_macro__width_2
File:sio_olc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_olc_ctl:ff_pq_wr_en , sio_olc_ctl:ff_ue_en , sio_olc_ctl:ff_slp_cycle , sio_olc_ctl:ff_payload_readys , sio_olc_ctl:ff_pq_rd_en 
 sio_olc_ctl_msff_ctl_macro__width_3
File:sio_olc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_olc_ctl:ff_hq_wr_ptr , sio_olc_ctl:ff_ue_wr_ptr , sio_olc_ctl:ff_hq_rd_ptr , sio_olc_ctl:ff_ue_rd_ptr 
 sio_olc_ctl_msff_ctl_macro__width_4
File:sio_olc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_olc_ctl:ff_ojc_cycle_sox , sio_olc_ctl:ff_ojc_ack_sox 
 sio_olc_ctl_msff_ctl_macro__width_6
File:sio_olc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_olc_ctl:ff_ojc_shcnt 
 sio_olc_ctl_msff_ctl_macro__width_7
File:sio_olc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_olc_ctl:ff_pq_wr_ptr , sio_olc_ctl:ff_pq_rd_ptr 
 sio_old_dp
File:sio_old_dp.v
Instantiates:sio_old_dp_mux_macro__mux_aope__ports_2__stack_46r__width_46:mx21_mbi_olddqx0 , sio_old_dp_mux_macro__mux_aope__ports_2__stack_46r__width_46:mx21_mbi_olddqx1 , sio_old_dp_msff_macro__stack_64c__width_35:dff_in_sol0 , sio_old_dp_prty_macro__width_16:prty_pgen1_sol0 , sio_old_dp_prty_macro__width_16:prty_pgen0_sol0 , sio_old_dp_xor_macro__left_1__stack_4r__width_1:xr2_perr1_sol0 , sio_old_dp_xor_macro__left_0__stack_4r__width_1:xr2_perr0_sol0 , sio_old_dp_inv_macro__left_0__stack_4r__width_1:inv_passperr_sol0 , sio_old_dp_nand_macro__left_0__stack_4r__width_1:nd2_olderr_sol0 , sio_old_dp_nor_macro__left_0__ports_3__stack_4r__width_1:nr3_setperr_sol0 , sio_old_dp_nand_macro__left_0__ports_2__stack_4r__width_1:nd2_perr_sol0 , sio_old_dp_msff_macro__left_0__stack_4r__width_1:eff_perr_sol1 , sio_old_dp_msff_macro__left_0__stack_2r__width_1:eff_ue0_sol2 , sio_old_dp_msff_macro__left_0__stack_2r__width_1:eff_ue1_sol2 , sio_old_dp_msff_macro__left_0__stack_2r__width_1:eff_ue2_sol2 , sio_old_dp_msff_macro__left_0__stack_2r__width_1:eff_ue3_sol2 , sio_old_dp_mux_macro__left_0__mux_pgdec__ports_4__stack_2r__width_1:mx41_ue41out , sio_old_dp_or_macro__stack_2l__width_1:or_ue , sio_old_dp_mux_macro__mux_pgpe__ports_2__stack_32l__width_32:mx21_old_opd_data , sio_old_dp_mux_macro__mux_pgdec__ports_4__stack_26l__width_26:hqout , sio_old_dp_msff_macro__stack_32l__width_30:ff_hqout , sio_old_dp_msff_macro__stack_26l__width_26:ff_hqmem0 , sio_old_dp_msff_macro__stack_26l__width_26:ff_hqmem1 , sio_old_dp_msff_macro__stack_26l__width_26:ff_hqmem2 , sio_old_dp_msff_macro__stack_26l__width_26:ff_hqmem3 , sio_old_dp_msff_macro__stack_32l__width_32:eff_jtagsr_h , sio_old_dp_msff_macro__stack_32l__width_32:eff_jtagsr_l , sio_old_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64:mx21_in_jtag_temp , sio_old_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64:mx21_in_jtag , sio_old_dp_prty_macro__width_16:ctag_syndrome0 , sio_old_dp_prty_macro__width_16:ctag_syndrome1 , sio_old_dp_prty_macro__width_16:ctag_syndrome2 , sio_old_dp_prty_macro__width_8:ctag_syndrome3 , sio_old_dp_prty_macro__width_8:ctag_syndrome4 , sio_old_dp_prty_macro__width_16:ctag_syndrome5 
Instantiated by:sio:old0 , sio:old1 , sio:old2 , sio:old3 , sio:old4 , sio:old5 , sio:old6 , sio:old7 
 sio_old_dp_inv_macro__left_0__stack_4r__width_1
File:sio_old_dp.v
Instantiates:inv:d0_0 
Instantiated by:sio_old_dp:inv_passperr_sol0 
 sio_old_dp_msff_macro__left_0__stack_2r__width_1
File:sio_old_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sio_old_dp:eff_ue0_sol2 , sio_old_dp:eff_ue1_sol2 , sio_old_dp:eff_ue2_sol2 , sio_old_dp:eff_ue3_sol2 
 sio_old_dp_msff_macro__left_0__stack_4r__width_1
File:sio_old_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sio_old_dp:eff_perr_sol1 
 sio_old_dp_msff_macro__stack_26l__width_26
File:sio_old_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sio_old_dp:ff_hqmem0 , sio_old_dp:ff_hqmem1 , sio_old_dp:ff_hqmem2 , sio_old_dp:ff_hqmem3 
 sio_old_dp_msff_macro__stack_32l__width_30
File:sio_old_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sio_old_dp:ff_hqout 
 sio_old_dp_msff_macro__stack_32l__width_32
File:sio_old_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sio_old_dp:eff_jtagsr_h , sio_old_dp:eff_jtagsr_l 
 sio_old_dp_msff_macro__stack_64c__width_35
File:sio_old_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sio_old_dp:dff_in_sol0 
 sio_old_dp_mux_macro__left_0__mux_pgdec__ports_4__stack_2r__width_1
File:sio_old_dp.v
Instantiates:cl_dp1_pdec4_8x:c0_0 , mux4:d0_0 
Instantiated by:sio_old_dp:mx41_ue41out 
 sio_old_dp_mux_macro__mux_aope__ports_2__stack_46r__width_46
File:sio_old_dp.v
Instantiates:cl_dp1_penc2_8x:c0_0 , mux2s:d0_0 
Instantiated by:sio_old_dp:mx21_mbi_olddqx0 , sio_old_dp:mx21_mbi_olddqx1 
 sio_old_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64
File:sio_old_dp.v
Instantiates:cl_dp1_penc2_8x:c0_0 , mux2s:d0_0 
Instantiated by:sio_old_dp:mx21_in_jtag_temp , sio_old_dp:mx21_in_jtag 
 sio_old_dp_mux_macro__mux_pgdec__ports_4__stack_26l__width_26
File:sio_old_dp.v
Instantiates:cl_dp1_pdec4_8x:c0_0 , mux4:d0_0 
Instantiated by:sio_old_dp:hqout 
 sio_old_dp_mux_macro__mux_pgpe__ports_2__stack_32l__width_32
File:sio_old_dp.v
Instantiates:cl_dp1_penc2_8x:c0_0 , mux2e:d0_0 
Instantiated by:sio_old_dp:mx21_old_opd_data 
 sio_old_dp_nand_macro__left_0__ports_2__stack_4r__width_1
File:sio_old_dp.v
Instantiates:nand2:d0_0 
Instantiated by:sio_old_dp:nd2_perr_sol0 
 sio_old_dp_nand_macro__left_0__stack_4r__width_1
File:sio_old_dp.v
Instantiates:nand2:d0_0 
Instantiated by:sio_old_dp:nd2_olderr_sol0 
 sio_old_dp_nor_macro__left_0__ports_3__stack_4r__width_1
File:sio_old_dp.v
Instantiates:nor3:d0_0 
Instantiated by:sio_old_dp:nr3_setperr_sol0 
 sio_old_dp_or_macro__stack_2l__width_1
File:sio_old_dp.v
Instantiates:or2:d0_0 
Instantiated by:sio_old_dp:or_ue 
 sio_old_dp_prty_macro__width_16
File:sio_old_dp.v
Instantiates:prty:m0_0 
Instantiated by:sio_old_dp:prty_pgen1_sol0 , sio_old_dp:prty_pgen0_sol0 , sio_old_dp:ctag_syndrome0 , sio_old_dp:ctag_syndrome1 , sio_old_dp:ctag_syndrome2 , sio_old_dp:ctag_syndrome5 
 sio_old_dp_prty_macro__width_8
File:sio_old_dp.v
Instantiates:prty:m0_0 
Instantiated by:sio_old_dp:ctag_syndrome3 , sio_old_dp:ctag_syndrome4 
 sio_old_dp_xor_macro__left_0__stack_4r__width_1
File:sio_old_dp.v
Instantiates:xor2:d0_0 
Instantiated by:sio_old_dp:xr2_perr0_sol0 
 sio_old_dp_xor_macro__left_1__stack_4r__width_1
File:sio_old_dp.v
Instantiates:xor2:d0_0 
Instantiated by:sio_old_dp:xr2_perr1_sol0 
 sio_opcc_ctl
File:sio_opcc_ctl.v
Instantiates:sio_opcc_ctl_l1clkhdr_ctl_macro:clkgen , sio_opcc_ctl_spare_ctl_macro__num_3:spares , sio_opcc_ctl_msff_ctl_macro__width_2:ff_tcu_jtag , sio_opcc_ctl_msff_ctl_macro__width_12:ff_dqcnt , sio_opcc_ctl_msff_ctl_macro__width_5:ff_syn_opdhq0_rd_addr , sio_opcc_ctl_msff_ctl_macro__width_5:ff_opdhq0_rd_addr , sio_opcc_ctl_msff_ctl_macro__width_5:ff_syn_opdhq1_rd_addr , sio_opcc_ctl_msff_ctl_macro__width_5:ff_opdhq1_rd_addr , sio_opcc_ctl_msff_ctl_macro__width_5:ff_opdhq0sub , sio_opcc_ctl_msff_ctl_macro__width_5:ff_opdhq1sub , sio_opcc_ctl_msff_ctl_macro__width_42:ff_slpstates , sio_opcc_ctl_msff_ctl_macro__width_3:ff_buscnt , sio_opcc_ctl_msff_ctl_macro__width_4:ff_hqxwonstage , sio_opcc_ctl_msff_ctl_macro__width_16:ff_qxdatastage , sio_opcc_ctl_msff_ctl_macro__width_5:ff_opdhq0_wr_addr , sio_opcc_ctl_msff_ctl_macro__width_5:ff_opdhq1_wr_addr , sio_opcc_ctl_msff_ctl_macro__width_7:ff_opddq00_wr_addr , sio_opcc_ctl_msff_ctl_macro__width_7:ff_opddq10_wr_addr , sio_opcc_ctl_msff_ctl_macro__width_7:ff_opddq01_wr_addr , sio_opcc_ctl_msff_ctl_macro__width_7:ff_opddq11_wr_addr , sio_opcc_ctl_msff_ctl_macro__width_1:ff_opddq00_wr_addrinc , sio_opcc_ctl_msff_ctl_macro__width_1:ff_opddq01_wr_addrinc , sio_opcc_ctl_msff_ctl_macro__width_1:ff_opddq10_wr_addrinc , sio_opcc_ctl_msff_ctl_macro__width_1:ff_opddq11_wr_addrinc , sio_opcc_ctl_msff_ctl_macro__width_7:ff_opddq00_wr_addr_d1 , sio_opcc_ctl_msff_ctl_macro__width_7:ff_syn_opddq00_wr_addr , sio_opcc_ctl_msff_ctl_macro__width_7:ff_opddq01_wr_addr_d1 , sio_opcc_ctl_msff_ctl_macro__width_7:ff_syn_opddq01_wr_addr , sio_opcc_ctl_msff_ctl_macro__width_7:ff_opddq10_wr_addr_d1 , sio_opcc_ctl_msff_ctl_macro__width_7:ff_syn_opddq10_wr_addr , sio_opcc_ctl_msff_ctl_macro__width_7:ff_opddq11_wr_addr_d1 , sio_opcc_ctl_msff_ctl_macro__width_7:ff_syn_opddq11_wr_addr , sio_opcc_ctl_msff_ctl_macro__width_5:ff_opdhq0_wr_addr_d1 , sio_opcc_ctl_msff_ctl_macro__width_5:ff_syn_opdhq0_wr_addr , sio_opcc_ctl_msff_ctl_macro__width_5:ff_opdhq1_wr_addr_d1 , sio_opcc_ctl_msff_ctl_macro__width_5:ff_syn_opdhq1_wr_addr , sio_opcc_ctl_msff_ctl_macro__width_1:ff_syn_opdhq0_wr_en_d1 , sio_opcc_ctl_msff_ctl_macro__en_1__width_1:ff_syn_opdhq0_wr_en_d2 , sio_opcc_ctl_msff_ctl_macro__width_1:ff_syn_opdhq1_wr_en_d1 , sio_opcc_ctl_msff_ctl_macro__width_1:ff_syn_opdhq1_wr_en_d2 , sio_opcc_ctl_msff_ctl_macro__width_1:reg_cmp_io_sync_en , sio_opcc_ctl_msff_ctl_macro__width_1:reg_io_cmp_sync_en 
Instantiated by:sio:opcc 
 sio_opcc_ctl_l1clkhdr_ctl_macro
File:sio_opcc_ctl.v
Instantiates:cl_sc1_l1hdr_8x:c_0 
Instantiated by:sio_opcc_ctl:clkgen 
 sio_opcc_ctl_msff_ctl_macro__en_1__width_1
File:sio_opcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_opcc_ctl:ff_syn_opdhq0_wr_en_d2 
 sio_opcc_ctl_msff_ctl_macro__width_1
File:sio_opcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_opcc_ctl:ff_opddq00_wr_addrinc , sio_opcc_ctl:ff_opddq01_wr_addrinc , sio_opcc_ctl:ff_opddq10_wr_addrinc , sio_opcc_ctl:ff_opddq11_wr_addrinc , sio_opcc_ctl:ff_syn_opdhq0_wr_en_d1 , sio_opcc_ctl:ff_syn_opdhq1_wr_en_d1 , sio_opcc_ctl:ff_syn_opdhq1_wr_en_d2 , sio_opcc_ctl:reg_cmp_io_sync_en , sio_opcc_ctl:reg_io_cmp_sync_en 
 sio_opcc_ctl_msff_ctl_macro__width_12
File:sio_opcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_opcc_ctl:ff_dqcnt 
 sio_opcc_ctl_msff_ctl_macro__width_16
File:sio_opcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_opcc_ctl:ff_qxdatastage 
 sio_opcc_ctl_msff_ctl_macro__width_2
File:sio_opcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_opcc_ctl:ff_tcu_jtag 
 sio_opcc_ctl_msff_ctl_macro__width_3
File:sio_opcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_opcc_ctl:ff_buscnt 
 sio_opcc_ctl_msff_ctl_macro__width_4
File:sio_opcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_opcc_ctl:ff_hqxwonstage 
 sio_opcc_ctl_msff_ctl_macro__width_42
File:sio_opcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_opcc_ctl:ff_slpstates 
 sio_opcc_ctl_msff_ctl_macro__width_5
File:sio_opcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_opcc_ctl:ff_syn_opdhq0_rd_addr , sio_opcc_ctl:ff_opdhq0_rd_addr , sio_opcc_ctl:ff_syn_opdhq1_rd_addr , sio_opcc_ctl:ff_opdhq1_rd_addr , sio_opcc_ctl:ff_opdhq0sub , sio_opcc_ctl:ff_opdhq1sub , sio_opcc_ctl:ff_opdhq0_wr_addr , sio_opcc_ctl:ff_opdhq1_wr_addr , sio_opcc_ctl:ff_opdhq0_wr_addr_d1 , sio_opcc_ctl:ff_syn_opdhq0_wr_addr , sio_opcc_ctl:ff_opdhq1_wr_addr_d1 , sio_opcc_ctl:ff_syn_opdhq1_wr_addr 
 sio_opcc_ctl_msff_ctl_macro__width_7
File:sio_opcc_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_opcc_ctl:ff_opddq00_wr_addr , sio_opcc_ctl:ff_opddq10_wr_addr , sio_opcc_ctl:ff_opddq01_wr_addr , sio_opcc_ctl:ff_opddq11_wr_addr , sio_opcc_ctl:ff_opddq00_wr_addr_d1 , sio_opcc_ctl:ff_syn_opddq00_wr_addr , sio_opcc_ctl:ff_opddq01_wr_addr_d1 , sio_opcc_ctl:ff_syn_opddq01_wr_addr , sio_opcc_ctl:ff_opddq10_wr_addr_d1 , sio_opcc_ctl:ff_syn_opddq10_wr_addr , sio_opcc_ctl:ff_opddq11_wr_addr_d1 , sio_opcc_ctl:ff_syn_opddq11_wr_addr 
 sio_opcc_ctl_spare_ctl_macro__num_3
File:sio_opcc_ctl.v
Instantiates:cl_sc1_msff_8x:spare0_flop , cl_u1_buf_32x:spare0_buf_32x , cl_u1_nand3_8x:spare0_nand3_8x , cl_u1_inv_8x:spare0_inv_8x , cl_u1_aoi22_4x:spare0_aoi22_4x , cl_u1_buf_8x:spare0_buf_8x , cl_u1_oai22_4x:spare0_oai22_4x , cl_u1_inv_16x:spare0_inv_16x , cl_u1_nand2_16x:spare0_nand2_16x , cl_u1_nor3_4x:spare0_nor3_4x , cl_u1_nand2_8x:spare0_nand2_8x , cl_u1_buf_16x:spare0_buf_16x , cl_u1_nor2_16x:spare0_nor2_16x , cl_u1_inv_32x:spare0_inv_32x , cl_sc1_msff_8x:spare1_flop , cl_u1_buf_32x:spare1_buf_32x , cl_u1_nand3_8x:spare1_nand3_8x , cl_u1_inv_8x:spare1_inv_8x , cl_u1_aoi22_4x:spare1_aoi22_4x , cl_u1_buf_8x:spare1_buf_8x , cl_u1_oai22_4x:spare1_oai22_4x , cl_u1_inv_16x:spare1_inv_16x , cl_u1_nand2_16x:spare1_nand2_16x , cl_u1_nor3_4x:spare1_nor3_4x , cl_u1_nand2_8x:spare1_nand2_8x , cl_u1_buf_16x:spare1_buf_16x , cl_u1_nor2_16x:spare1_nor2_16x , cl_u1_inv_32x:spare1_inv_32x , cl_sc1_msff_8x:spare2_flop , cl_u1_buf_32x:spare2_buf_32x , cl_u1_nand3_8x:spare2_nand3_8x , cl_u1_inv_8x:spare2_inv_8x , cl_u1_aoi22_4x:spare2_aoi22_4x , cl_u1_buf_8x:spare2_buf_8x , cl_u1_oai22_4x:spare2_oai22_4x , cl_u1_inv_16x:spare2_inv_16x , cl_u1_nand2_16x:spare2_nand2_16x , cl_u1_nor3_4x:spare2_nor3_4x , cl_u1_nand2_8x:spare2_nand2_8x , cl_u1_buf_16x:spare2_buf_16x , cl_u1_nor2_16x:spare2_nor2_16x , cl_u1_inv_32x:spare2_inv_32x 
Instantiated by:sio_opcc_ctl:spares 
 sio_opcs_ctl
File:sio_opcs_ctl.v
Instantiates:sio_opcs_ctl_l1clkhdr_ctl_macro:clkgen , sio_opcs_ctl_spare_ctl_macro__num_2:spares , sio_opcs_ctl_msff_ctl_macro__width_8:reg_cstate , sio_opcs_ctl_msff_ctl_macro__width_1:reg_packet_req , sio_opcs_ctl_msff_ctl_macro__width_1:reg_packet_datareq , sio_opcs_ctl_msff_ctl_macro__width_7:reg_opddqx0_rd_addr , sio_opcs_ctl_msff_ctl_macro__width_7:reg_opddqx1_rd_addr , sio_opcs_ctl_msff_ctl_macro__width_5:reg_opdhqx_rd_addr , sio_opcs_ctl_msff_ctl_macro__width_5:reg_opcs_opcc_opdhqx_rd_addr , sio_opcs_ctl_msff_ctl_macro__width_3:reg_crd_cnt , sio_opcs_ctl_msff_ctl_macro__width_5:reg_opdhqx_wr_addr , sio_opcs_ctl_msff_ctl_macro__width_7:reg_opddqx0_wr_addr , sio_opcs_ctl_msff_ctl_macro__width_7:reg_opddqx1_wr_addr , sio_opcs_ctl_msff_ctl_macro__width_1:reg_valid , sio_opcs_ctl_msff_ctl_macro__width_1:reg_opdhqx_ue_bit , sio_opcs_ctl_msff_ctl_macro__width_1:reg_hq_almost_r , sio_opcs_ctl_msff_ctl_macro__width_1:reg_ncu_ctag_ue , sio_opcs_ctl_msff_ctl_macro__width_1:reg_ncu_ctag_ce , sio_opcs_ctl_msff_ctl_macro__width_1:reg_ncu_d_pe 
Instantiated by:sio:opcs0 , sio:opcs1 
 sio_opcs_ctl_l1clkhdr_ctl_macro
File:sio_opcs_ctl.v
Instantiates:cl_sc1_l1hdr_8x:c_0 
Instantiated by:sio_opcs_ctl:clkgen 
 sio_opcs_ctl_msff_ctl_macro__width_1
File:sio_opcs_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_opcs_ctl:reg_packet_req , sio_opcs_ctl:reg_packet_datareq , sio_opcs_ctl:reg_valid , sio_opcs_ctl:reg_opdhqx_ue_bit , sio_opcs_ctl:reg_hq_almost_r , sio_opcs_ctl:reg_ncu_ctag_ue , sio_opcs_ctl:reg_ncu_ctag_ce , sio_opcs_ctl:reg_ncu_d_pe 
 sio_opcs_ctl_msff_ctl_macro__width_3
File:sio_opcs_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_opcs_ctl:reg_crd_cnt 
 sio_opcs_ctl_msff_ctl_macro__width_5
File:sio_opcs_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_opcs_ctl:reg_opdhqx_rd_addr , sio_opcs_ctl:reg_opcs_opcc_opdhqx_rd_addr , sio_opcs_ctl:reg_opdhqx_wr_addr 
 sio_opcs_ctl_msff_ctl_macro__width_7
File:sio_opcs_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_opcs_ctl:reg_opddqx0_rd_addr , sio_opcs_ctl:reg_opddqx1_rd_addr , sio_opcs_ctl:reg_opddqx0_wr_addr , sio_opcs_ctl:reg_opddqx1_wr_addr 
 sio_opcs_ctl_msff_ctl_macro__width_8
File:sio_opcs_ctl.v
Instantiates:dff:d0_0 
Instantiated by:sio_opcs_ctl:reg_cstate 
 sio_opcs_ctl_spare_ctl_macro__num_2
File:sio_opcs_ctl.v
Instantiates:cl_sc1_msff_8x:spare0_flop , cl_u1_buf_32x:spare0_buf_32x , cl_u1_nand3_8x:spare0_nand3_8x , cl_u1_inv_8x:spare0_inv_8x , cl_u1_aoi22_4x:spare0_aoi22_4x , cl_u1_buf_8x:spare0_buf_8x , cl_u1_oai22_4x:spare0_oai22_4x , cl_u1_inv_16x:spare0_inv_16x , cl_u1_nand2_16x:spare0_nand2_16x , cl_u1_nor3_4x:spare0_nor3_4x , cl_u1_nand2_8x:spare0_nand2_8x , cl_u1_buf_16x:spare0_buf_16x , cl_u1_nor2_16x:spare0_nor2_16x , cl_u1_inv_32x:spare0_inv_32x , cl_sc1_msff_8x:spare1_flop , cl_u1_buf_32x:spare1_buf_32x , cl_u1_nand3_8x:spare1_nand3_8x , cl_u1_inv_8x:spare1_inv_8x , cl_u1_aoi22_4x:spare1_aoi22_4x , cl_u1_buf_8x:spare1_buf_8x , cl_u1_oai22_4x:spare1_oai22_4x , cl_u1_inv_16x:spare1_inv_16x , cl_u1_nand2_16x:spare1_nand2_16x , cl_u1_nor3_4x:spare1_nor3_4x , cl_u1_nand2_8x:spare1_nand2_8x , cl_u1_buf_16x:spare1_buf_16x , cl_u1_nor2_16x:spare1_nor2_16x , cl_u1_inv_32x:spare1_inv_32x 
Instantiated by:sio_opcs_ctl:spares 
 sio_opdc_dp
File:sio_opdc_dp.v
Instantiates:sio_opdc_dp_mux_macro__mux_pgpe__ports_2__stack_66c__width_66:mx21_bank01_data , sio_opdc_dp_buff_macro__minbuff_1__stack_2l__width_2:buf_mx21_bank01_data , sio_opdc_dp_mux_macro__mux_pgpe__ports_2__stack_66c__width_66:mx21_bank23_data , sio_opdc_dp_mux_macro__mux_pgpe__ports_2__stack_66c__width_66:mx21_bank45_data , sio_opdc_dp_buff_macro__minbuff_1__stack_12l__width_12:buf_mx21_bank45_data , sio_opdc_dp_mux_macro__mux_pgpe__ports_2__stack_66c__width_66:mx21_bank67_data , sio_opdc_dp_mux_macro__dmux_16x__mux_pgpe__ports_2__stack_68c__width_68:mx21_mbist01_data , sio_opdc_dp_mux_macro__dmux_16x__mux_pgpe__ports_2__stack_68c__width_68:mx21_mbist23_data , sio_opdc_dp_mux_macro__dmux_16x__mux_pgpe__ports_2__stack_68c__width_68:mx21_mbist45_data , sio_opdc_dp_mux_macro__dmux_16x__mux_pgpe__ports_2__stack_68c__width_68:mx21_mbist67_data , sio_opdc_dp_mux_macro__dmux_16x__mux_pgpe__ports_2__stack_68c__width_68:mx21_mbist0145_data , sio_opdc_dp_msff_macro__stack_34l__width_34:dff_mbist0145_data_h , sio_opdc_dp_msff_macro__stack_34l__width_34:dff_mbist0145_data_l , sio_opdc_dp_mux_macro__dmux_16x__mux_pgpe__ports_2__stack_68c__width_68:mx21_mbist2367_data , sio_opdc_dp_msff_macro__stack_34l__width_34:dff_mbist2367_data_h , sio_opdc_dp_msff_macro__stack_34l__width_34:dff_mbist2367_data_l , sio_opdc_dp_buff_macro__minbuff_1__stack_10l__width_10:buf_bank01_data_opc1_h0 , sio_opdc_dp_msff_macro__stack_34l__width_34:dff_bank01_data_opc1_h , sio_opdc_dp_msff_macro__stack_32l__width_32:dff_bank01_data_opc1_l , sio_opdc_dp_msff_macro__stack_34l__width_34:dff_bank23_data_opc1_h , sio_opdc_dp_msff_macro__stack_32l__width_32:dff_bank23_data_opc1_l , sio_opdc_dp_buff_macro__minbuff_1__stack_6l__width_6:buf_bank45_data_opc1_h , sio_opdc_dp_msff_macro__stack_34l__width_34:dff_bank45_data_opc1_h , sio_opdc_dp_msff_macro__stack_32l__width_32:dff_bank45_data_opc1_l , sio_opdc_dp_buff_macro__minbuff_1__stack_18l__width_18:buf_bank67_data_opc1_h , sio_opdc_dp_msff_macro__stack_34l__width_34:dff_bank67_data_opc1_h , sio_opdc_dp_msff_macro__stack_32l__width_32:dff_bank67_data_opc1_l , sio_opdc_dp_prty_macro__width_16:prty_bank01_parity3 , sio_opdc_dp_prty_macro__width_16:prty_bank01_parity2 , sio_opdc_dp_prty_macro__width_16:prty_bank01_parity1 , sio_opdc_dp_prty_macro__width_16:prty_bank01_parity0 , sio_opdc_dp_prty_macro__width_16:prty_bank23_parity3 , sio_opdc_dp_prty_macro__width_16:prty_bank23_parity2 , sio_opdc_dp_prty_macro__width_16:prty_bank23_parity1 , sio_opdc_dp_prty_macro__width_16:prty_bank23_parity0 , sio_opdc_dp_prty_macro__width_16:prty_bank45_parity3 , sio_opdc_dp_prty_macro__width_16:prty_bank45_parity2 , sio_opdc_dp_prty_macro__width_16:prty_bank45_parity1 , sio_opdc_dp_prty_macro__width_16:prty_bank45_parity0 , sio_opdc_dp_prty_macro__width_16:prty_bank67_parity3 , sio_opdc_dp_prty_macro__width_16:prty_bank67_parity2 , sio_opdc_dp_prty_macro__width_16:prty_bank67_parity1 , sio_opdc_dp_prty_macro__width_16:prty_bank67_parity0 , sio_opdc_dp_xor_macro__width_4:bank01_parity_ue , sio_opdc_dp_xor_macro__width_4:bank23_parity_ue , sio_opdc_dp_xor_macro__width_4:bank45_parity_ue , sio_opdc_dp_xor_macro__width_4:bank67_parity_ue , sio_opdc_dp_mux_macro__mux_pgpe__ports_2__stack_64c__width_64:mx21_bankleft_data , sio_opdc_dp_mux_macro__mux_pgpe__ports_2__stack_64c__width_64:mx21_bankright_data , sio_opdc_dp_mux_macro__mux_pgnpe__ports_4__stack_4c__width_4:mx21_bank_parity , sio_opdc_dp_inv_macro__width_3:inv_sel_bank_parity , sio_opdc_dp_and_macro__left_0__ports_2__stack_4r__width_4:and_left_right_4567 , sio_opdc_dp_mux_macro__mux_pgpe__ports_2__stack_64c__width_64:mx21_bank_data , sio_opdc_dp_mux_macro__dmux_8x__mux_pgpe__ports_2__stack_72c__width_72:mx21_mb1bank_dataparity , sio_opdc_dp_mux_macro__mux_aope__ports_2__stack_38c__width_38:mx21_mbist_write_controls 
Instantiated by:sio:opdc 
 sio_opdc_dp_and_macro__left_0__ports_2__stack_4r__width_4
File:sio_opdc_dp.v
Instantiates:and2:d0_0 
Instantiated by:sio_opdc_dp:and_left_right_4567 
 sio_opdc_dp_buff_macro__minbuff_1__stack_10l__width_10
File:sio_opdc_dp.v
Instantiates:buff:d0_0 
Instantiated by:sio_opdc_dp:buf_bank01_data_opc1_h0 
 sio_opdc_dp_buff_macro__minbuff_1__stack_12l__width_12
File:sio_opdc_dp.v
Instantiates:buff:d0_0 
Instantiated by:sio_opdc_dp:buf_mx21_bank45_data 
 sio_opdc_dp_buff_macro__minbuff_1__stack_18l__width_18
File:sio_opdc_dp.v
Instantiates:buff:d0_0 
Instantiated by:sio_opdc_dp:buf_bank67_data_opc1_h 
 sio_opdc_dp_buff_macro__minbuff_1__stack_2l__width_2
File:sio_opdc_dp.v
Instantiates:buff:d0_0 
Instantiated by:sio_opdc_dp:buf_mx21_bank01_data 
 sio_opdc_dp_buff_macro__minbuff_1__stack_6l__width_6
File:sio_opdc_dp.v
Instantiates:buff:d0_0 
Instantiated by:sio_opdc_dp:buf_bank45_data_opc1_h 
 sio_opdc_dp_inv_macro__width_3
File:sio_opdc_dp.v
Instantiates:inv:d0_0 
Instantiated by:sio_opdc_dp:inv_sel_bank_parity 
 sio_opdc_dp_msff_macro__stack_32l__width_32
File:sio_opdc_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sio_opdc_dp:dff_bank01_data_opc1_l , sio_opdc_dp:dff_bank23_data_opc1_l , sio_opdc_dp:dff_bank45_data_opc1_l , sio_opdc_dp:dff_bank67_data_opc1_l 
 sio_opdc_dp_msff_macro__stack_34l__width_34
File:sio_opdc_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sio_opdc_dp:dff_mbist0145_data_h , sio_opdc_dp:dff_mbist0145_data_l , sio_opdc_dp:dff_mbist2367_data_h , sio_opdc_dp:dff_mbist2367_data_l , sio_opdc_dp:dff_bank01_data_opc1_h , sio_opdc_dp:dff_bank23_data_opc1_h , sio_opdc_dp:dff_bank45_data_opc1_h , sio_opdc_dp:dff_bank67_data_opc1_h 
 sio_opdc_dp_mux_macro__dmux_16x__mux_pgpe__ports_2__stack_68c__width_68
File:sio_opdc_dp.v
Instantiates:cl_dp1_penc2_8x:c0_0 , mux2e:d0_0 
Instantiated by:sio_opdc_dp:mx21_mbist01_data , sio_opdc_dp:mx21_mbist23_data , sio_opdc_dp:mx21_mbist45_data , sio_opdc_dp:mx21_mbist67_data , sio_opdc_dp:mx21_mbist0145_data , sio_opdc_dp:mx21_mbist2367_data 
 sio_opdc_dp_mux_macro__dmux_8x__mux_pgpe__ports_2__stack_72c__width_72
File:sio_opdc_dp.v
Instantiates:cl_dp1_penc2_8x:c0_0 , mux2e:d0_0 
Instantiated by:sio_opdc_dp:mx21_mb1bank_dataparity 
 sio_opdc_dp_mux_macro__mux_aope__ports_2__stack_38c__width_38
File:sio_opdc_dp.v
Instantiates:cl_dp1_penc2_8x:c0_0 , mux2s:d0_0 
Instantiated by:sio_opdc_dp:mx21_mbist_write_controls 
 sio_opdc_dp_mux_macro__mux_pgnpe__ports_4__stack_4c__width_4
File:sio_opdc_dp.v
Instantiates:cl_dp1_muxbuff4_8x:c0_0 , mux4:d0_0 
Instantiated by:sio_opdc_dp:mx21_bank_parity 
 sio_opdc_dp_mux_macro__mux_pgpe__ports_2__stack_64c__width_64
File:sio_opdc_dp.v
Instantiates:cl_dp1_penc2_8x:c0_0 , mux2e:d0_0 
Instantiated by:sio_opdc_dp:mx21_bankleft_data , sio_opdc_dp:mx21_bankright_data , sio_opdc_dp:mx21_bank_data 
 sio_opdc_dp_mux_macro__mux_pgpe__ports_2__stack_66c__width_66
File:sio_opdc_dp.v
Instantiates:cl_dp1_penc2_8x:c0_0 , mux2e:d0_0 
Instantiated by:sio_opdc_dp:mx21_bank01_data , sio_opdc_dp:mx21_bank23_data , sio_opdc_dp:mx21_bank45_data , sio_opdc_dp:mx21_bank67_data 
 sio_opdc_dp_prty_macro__width_16
File:sio_opdc_dp.v
Instantiates:prty:m0_0 
Instantiated by:sio_opdc_dp:prty_bank01_parity3 , sio_opdc_dp:prty_bank01_parity2 , sio_opdc_dp:prty_bank01_parity1 , sio_opdc_dp:prty_bank01_parity0 , sio_opdc_dp:prty_bank23_parity3 , sio_opdc_dp:prty_bank23_parity2 , sio_opdc_dp:prty_bank23_parity1 , sio_opdc_dp:prty_bank23_parity0 , sio_opdc_dp:prty_bank45_parity3 , sio_opdc_dp:prty_bank45_parity2 , sio_opdc_dp:prty_bank45_parity1 , sio_opdc_dp:prty_bank45_parity0 , sio_opdc_dp:prty_bank67_parity3 , sio_opdc_dp:prty_bank67_parity2 , sio_opdc_dp:prty_bank67_parity1 , sio_opdc_dp:prty_bank67_parity0 
 sio_opdc_dp_xor_macro__width_4
File:sio_opdc_dp.v
Instantiates:xor2:d0_0 
Instantiated by:sio_opdc_dp:bank01_parity_ue , sio_opdc_dp:bank23_parity_ue , sio_opdc_dp:bank45_parity_ue , sio_opdc_dp:bank67_parity_ue 
 sio_opds_dp
File:sio_opds_dp.v
Instantiates:sio_opds_dp_msff_macro__stack_32l__width_32:ff_packet_data0_h , sio_opds_dp_msff_macro__stack_32l__width_32:ff_packet_data0_l , sio_opds_dp_msff_macro__stack_32l__width_32:ff_packet_data1_h , sio_opds_dp_msff_macro__stack_32l__width_32:ff_packet_data1_l , sio_opds_dp_buff_macro__minbuff_1__stack_4l__width_4:buf_packet_parity , sio_opds_dp_msff_macro__left_32__stack_64c__width_8:ff_packet_parity , sio_opds_dp_xor_macro__ports_2__stack_8r__width_8:xor_compare , sio_opds_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64:mx21_opds_qx0_data , sio_opds_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64:mx21_opds_qx1_data , sio_opds_dp_xor_macro__left_1__stack_4r__width_1:xor2_err_inj_lsb , sio_opds_dp_prty_macro__width_16:prty_pgenx03 , sio_opds_dp_prty_macro__width_16:prty_pgenx02 , sio_opds_dp_prty_macro__width_16:prty_pgenx01 , sio_opds_dp_prty_macro__width_16:prty_pgenx00 , sio_opds_dp_prty_macro__width_16:prty_pgenx13 , sio_opds_dp_prty_macro__width_16:prty_pgenx12 , sio_opds_dp_prty_macro__width_16:prty_pgenx11 , sio_opds_dp_prty_macro__width_16:prty_pgenx10 , sio_opds_dp_inv_macro__left_0__stack_8l__width_8:inv_prty_pgenxyz , sio_opds_dp_msff_macro__stack_64c__width_32:ff_opdhqxout , sio_opds_dp_mux_macro__mux_aonpe__ports_3__stack_72c__width_72:mx31_mbist_read_data , sio_opds_dp_mux_macro__mux_aope__ports_2__stack_20c__width_20:mx21_mbist_read_controls 
Instantiated by:sio:opds0 , sio:opds1 
 sio_opds_dp_buff_macro__minbuff_1__stack_4l__width_4
File:sio_opds_dp.v
Instantiates:buff:d0_0 
Instantiated by:sio_opds_dp:buf_packet_parity 
 sio_opds_dp_inv_macro__left_0__stack_8l__width_8
File:sio_opds_dp.v
Instantiates:inv:d0_0 
Instantiated by:sio_opds_dp:inv_prty_pgenxyz 
 sio_opds_dp_msff_macro__left_32__stack_64c__width_8
File:sio_opds_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sio_opds_dp:ff_packet_parity 
 sio_opds_dp_msff_macro__stack_32l__width_32
File:sio_opds_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sio_opds_dp:ff_packet_data0_h , sio_opds_dp:ff_packet_data0_l , sio_opds_dp:ff_packet_data1_h , sio_opds_dp:ff_packet_data1_l 
 sio_opds_dp_msff_macro__stack_64c__width_32
File:sio_opds_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sio_opds_dp:ff_opdhqxout 
 sio_opds_dp_mux_macro__mux_aonpe__ports_3__stack_72c__width_72
File:sio_opds_dp.v
Instantiates:cl_dp1_muxbuff3_8x:c0_0 , mux3s:d0_0 
Instantiated by:sio_opds_dp:mx31_mbist_read_data 
 sio_opds_dp_mux_macro__mux_aope__ports_2__stack_20c__width_20
File:sio_opds_dp.v
Instantiates:cl_dp1_penc2_8x:c0_0 , mux2s:d0_0 
Instantiated by:sio_opds_dp:mx21_mbist_read_controls 
 sio_opds_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64
File:sio_opds_dp.v
Instantiates:cl_dp1_penc2_8x:c0_0 , mux2s:d0_0 
Instantiated by:sio_opds_dp:mx21_opds_qx0_data , sio_opds_dp:mx21_opds_qx1_data 
 sio_opds_dp_prty_macro__width_16
File:sio_opds_dp.v
Instantiates:prty:m0_0 
Instantiated by:sio_opds_dp:prty_pgenx03 , sio_opds_dp:prty_pgenx02 , sio_opds_dp:prty_pgenx01 , sio_opds_dp:prty_pgenx00 , sio_opds_dp:prty_pgenx13 , sio_opds_dp:prty_pgenx12 , sio_opds_dp:prty_pgenx11 , sio_opds_dp:prty_pgenx10 
 sio_opds_dp_xor_macro__left_1__stack_4r__width_1
File:sio_opds_dp.v
Instantiates:xor2:d0_0 
Instantiated by:sio_opds_dp:xor2_err_inj_lsb 
 sio_opds_dp_xor_macro__ports_2__stack_8r__width_8
File:sio_opds_dp.v
Instantiates:xor2:d0_0 
Instantiated by:sio_opds_dp:xor_compare 
 sio_stg1_dp
File:sio_stg1_dp.v
Instantiates:sio_stg1_dp_msff_macro__stack_36c__width_36:dff_l2b_sio_data 
Instantiated by:sio:stg1 , sio:stg2 , sio:stg3 , sio:stg4 
 sio_stg1_dp_msff_macro__stack_36c__width_36
File:sio_stg1_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sio_stg1_dp:dff_l2b_sio_data 
 sio_stg2_dp
File:sio_stg2_dp.v
Instantiates:sio_stg2_dp_msff_macro__stack_36c__width_36:dff_l2b_sio_data , sio_stg2_dp_msff_macro__stack_36c__width_36:dff_l2b_sio_data_2 
Instantiated by:sio:stg5 , sio:stg6 , sio:stg7 
 sio_stg2_dp_msff_macro__stack_36c__width_36
File:sio_stg2_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:sio_stg2_dp:dff_l2b_sio_data , sio_stg2_dp:dff_l2b_sio_data_2 
 socras_mon
File:iosras_mon.v
 sop_sm
File:sop_sm.v
Instantiates:RegRst:sop_state_RegRst 
Instantiated by:rx_xmac:sop_sm 
 spare_ctl_macro__num_4
File:n2_efuhdr1_ctl.v
Instantiates:cl_sc1_msff_8x:spare0_flop , cl_u1_buf_32x:spare0_buf_32x , cl_u1_nand3_8x:spare0_nand3_8x , cl_u1_inv_8x:spare0_inv_8x , cl_u1_aoi22_4x:spare0_aoi22_4x , cl_u1_buf_8x:spare0_buf_8x , cl_u1_oai22_4x:spare0_oai22_4x , cl_u1_inv_16x:spare0_inv_16x , cl_u1_nand2_16x:spare0_nand2_16x , cl_u1_nor3_4x:spare0_nor3_4x , cl_u1_nand2_8x:spare0_nand2_8x , cl_u1_buf_16x:spare0_buf_16x , cl_u1_nor2_16x:spare0_nor2_16x , cl_u1_inv_32x:spare0_inv_32x , cl_sc1_msff_8x:spare1_flop , cl_u1_buf_32x:spare1_buf_32x , cl_u1_nand3_8x:spare1_nand3_8x , cl_u1_inv_8x:spare1_inv_8x , cl_u1_aoi22_4x:spare1_aoi22_4x , cl_u1_buf_8x:spare1_buf_8x , cl_u1_oai22_4x:spare1_oai22_4x , cl_u1_inv_16x:spare1_inv_16x , cl_u1_nand2_16x:spare1_nand2_16x , cl_u1_nor3_4x:spare1_nor3_4x , cl_u1_nand2_8x:spare1_nand2_8x , cl_u1_buf_16x:spare1_buf_16x , cl_u1_nor2_16x:spare1_nor2_16x , cl_u1_inv_32x:spare1_inv_32x , cl_sc1_msff_8x:spare2_flop , cl_u1_buf_32x:spare2_buf_32x , cl_u1_nand3_8x:spare2_nand3_8x , cl_u1_inv_8x:spare2_inv_8x , cl_u1_aoi22_4x:spare2_aoi22_4x , cl_u1_buf_8x:spare2_buf_8x , cl_u1_oai22_4x:spare2_oai22_4x , cl_u1_inv_16x:spare2_inv_16x , cl_u1_nand2_16x:spare2_nand2_16x , cl_u1_nor3_4x:spare2_nor3_4x , cl_u1_nand2_8x:spare2_nand2_8x , cl_u1_buf_16x:spare2_buf_16x , cl_u1_nor2_16x:spare2_nor2_16x , cl_u1_inv_32x:spare2_inv_32x , cl_sc1_msff_8x:spare3_flop , cl_u1_buf_32x:spare3_buf_32x , cl_u1_nand3_8x:spare3_nand3_8x , cl_u1_inv_8x:spare3_inv_8x , cl_u1_aoi22_4x:spare3_aoi22_4x , cl_u1_buf_8x:spare3_buf_8x , cl_u1_oai22_4x:spare3_oai22_4x , cl_u1_inv_16x:spare3_inv_16x , cl_u1_nand2_16x:spare3_nand2_16x , cl_u1_nor3_4x:spare3_nor3_4x , cl_u1_nand2_8x:spare3_nand2_8x , cl_u1_buf_16x:spare3_buf_16x , cl_u1_nor2_16x:spare3_nor2_16x , cl_u1_inv_32x:spare3_inv_32x 
Instantiated by:n2_efuhdr1_ctl:spares_cmp 
 spc
File:spc.v
Instantiates:spc_rep1_dp:rep1 , spc_msf0_dp:msf0 , spc_msf1_dp:msf1 , spc_lb_ctl:lb , clkgen_spc_cmp:clk_spc , dmo_dp:dmo , gkt:gkt , fgu:fgu , ifu_ibu:ifu_ibu , ifu_ftu:ifu_ftu , ifu_cmu:ifu_cmu , dec:dec , pku:pku , exu:exu0 , exu:exu1 , exu_mdp_dp:mdp , tlu:tlu , lsu:lsu , spu:spu , mmu:mmu , pmu:pmu , spc_mb0_ctl:mb0 , spc_mb1_ctl:mb1 , spc_mb2_ctl:mb2 
Instantiated by:cpu:spc0 , cpu:spc1 , cpu:spc2 , cpu:spc3 , cpu:spc4 , cpu:spc5 , cpu:spc6 , cpu:spc7 
 spc_lb_ctl
File:spc_lb_ctl.v
Instantiates:spc_lb_ctll1clkhdr_ctl_macro:lbist_clkgen , cl_u1_buf_4x:lbist_clkbuf , spc_lb_ctll1clkhdr_ctl_macro:lbist_frclkgen , spc_lb_ctlmsff_ctl_macro__width_1:lb_clkstop_reg , spc_lb_ctlmsff_ctl_macro__width_1:lb_iocmpsyncen_reg , spc_lb_ctlmsff_ctl_macro__width_5:lb_control_reg , spc_lb_ctlmsff_ctl_macro__width_15:lb_shftpgm_reg , spc_lb_ctlmsff_ctl_macro__width_19:lb_shftcnt_reg , spc_lb_ctlmsff_ctl_macro__width_5:lb_capclkcnt_reg , spc_lb_ctlmsff_ctl_macro__width_16:lb_vectpgm_reg , spc_lb_ctlmsff_ctl_macro__width_16:lb_vectorcnt_reg , spc_lb_ctlmsff_ctl_macro__width_24:lb_prpg_reg , spc_lb_ctlmsff_ctl_macro__width_24:lb_misr_reg , spc_lb_ctlmsff_ctl_macro__width_16:lb_cb_reg , spc_lb_ctlmsff_ctl_macro__en_1__width_1:lb_done_reg , spc_lb_ctlspare_ctl_macro__num_3:spare 
Instantiated by:spc:lb 
 spc_lb_ctll1clkhdr_ctl_macro
File:spc_lb_ctl.v
Instantiates:cl_sc1_l1hdr_8x:c_0 
Instantiated by:spc_lb_ctl:lbist_clkgen , spc_lb_ctl:lbist_frclkgen 
 spc_lb_ctlmsff_ctl_macro__en_1__width_1
File:spc_lb_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_lb_ctl:lb_done_reg 
 spc_lb_ctlmsff_ctl_macro__width_1
File:spc_lb_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_lb_ctl:lb_clkstop_reg , spc_lb_ctl:lb_iocmpsyncen_reg 
 spc_lb_ctlmsff_ctl_macro__width_15
File:spc_lb_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_lb_ctl:lb_shftpgm_reg 
 spc_lb_ctlmsff_ctl_macro__width_16
File:spc_lb_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_lb_ctl:lb_vectpgm_reg , spc_lb_ctl:lb_vectorcnt_reg , spc_lb_ctl:lb_cb_reg 
 spc_lb_ctlmsff_ctl_macro__width_19
File:spc_lb_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_lb_ctl:lb_shftcnt_reg 
 spc_lb_ctlmsff_ctl_macro__width_24
File:spc_lb_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_lb_ctl:lb_prpg_reg , spc_lb_ctl:lb_misr_reg 
 spc_lb_ctlmsff_ctl_macro__width_5
File:spc_lb_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_lb_ctl:lb_control_reg , spc_lb_ctl:lb_capclkcnt_reg 
 spc_lb_ctlspare_ctl_macro__num_3
File:spc_lb_ctl.v
Instantiates:cl_sc1_msff_8x:spare0_flop , cl_u1_buf_32x:spare0_buf_32x , cl_u1_nand3_8x:spare0_nand3_8x , cl_u1_inv_8x:spare0_inv_8x , cl_u1_aoi22_4x:spare0_aoi22_4x , cl_u1_buf_8x:spare0_buf_8x , cl_u1_oai22_4x:spare0_oai22_4x , cl_u1_inv_16x:spare0_inv_16x , cl_u1_nand2_16x:spare0_nand2_16x , cl_u1_nor3_4x:spare0_nor3_4x , cl_u1_nand2_8x:spare0_nand2_8x , cl_u1_buf_16x:spare0_buf_16x , cl_u1_nor2_16x:spare0_nor2_16x , cl_u1_inv_32x:spare0_inv_32x , cl_sc1_msff_8x:spare1_flop , cl_u1_buf_32x:spare1_buf_32x , cl_u1_nand3_8x:spare1_nand3_8x , cl_u1_inv_8x:spare1_inv_8x , cl_u1_aoi22_4x:spare1_aoi22_4x , cl_u1_buf_8x:spare1_buf_8x , cl_u1_oai22_4x:spare1_oai22_4x , cl_u1_inv_16x:spare1_inv_16x , cl_u1_nand2_16x:spare1_nand2_16x , cl_u1_nor3_4x:spare1_nor3_4x , cl_u1_nand2_8x:spare1_nand2_8x , cl_u1_buf_16x:spare1_buf_16x , cl_u1_nor2_16x:spare1_nor2_16x , cl_u1_inv_32x:spare1_inv_32x , cl_sc1_msff_8x:spare2_flop , cl_u1_buf_32x:spare2_buf_32x , cl_u1_nand3_8x:spare2_nand3_8x , cl_u1_inv_8x:spare2_inv_8x , cl_u1_aoi22_4x:spare2_aoi22_4x , cl_u1_buf_8x:spare2_buf_8x , cl_u1_oai22_4x:spare2_oai22_4x , cl_u1_inv_16x:spare2_inv_16x , cl_u1_nand2_16x:spare2_nand2_16x , cl_u1_nor3_4x:spare2_nor3_4x , cl_u1_nand2_8x:spare2_nand2_8x , cl_u1_buf_16x:spare2_buf_16x , cl_u1_nor2_16x:spare2_nor2_16x , cl_u1_inv_32x:spare2_inv_32x 
Instantiated by:spc_lb_ctl:spare 
 spc_mb0_ctl
File:spc_mb0_ctl.v
Instantiates:spc_mb0_ctll1clkhdr_ctl_macro:clkgen , spc_mb0_ctlmsff_ctl_macro__width_3:pmen , spc_mb0_ctll1clkhdr_ctl_macro:clkgen_pm1 , spc_mb0_ctlmsff_ctl_macro__width_4:array_usr_reg , spc_mb0_ctlmsff_ctl_macro__width_1:user_addr_mode_reg , spc_mb0_ctlmsff_ctl_macro__width_9:user_start_addr_reg , spc_mb0_ctlmsff_ctl_macro__width_9:user_stop_addr_reg , spc_mb0_ctlmsff_ctl_macro__width_9:user_incr_addr_reg , spc_mb0_ctlmsff_ctl_macro__width_1:user_data_mode_reg , spc_mb0_ctlmsff_ctl_macro__width_8:user_data_reg , spc_mb0_ctlmsff_ctl_macro__width_1:user_cmpselinc_hold_reg , spc_mb0_ctlmsff_ctl_macro__width_3:user_cmpsel_reg , spc_mb0_ctlmsff_ctl_macro__width_1:user_loop_mode_reg , spc_mb0_ctlmsff_ctl_macro__width_1:ten_n_mode_reg , spc_mb0_ctlmsff_ctl_macro__width_1:user_cam_mode_reg , spc_mb0_ctlmsff_ctl_macro__width_2:user_cam_select_reg , spc_mb0_ctlmsff_ctl_macro__width_4:user_cam_test_select_reg , spc_mb0_ctlmsff_ctl_macro__width_1:user_bisi_wr_mode_reg , spc_mb0_ctlmsff_ctl_macro__width_1:user_bisi_rd_mode_reg , spc_mb0_ctlmsff_ctl_macro__width_2:input_signals_reg , spc_mb0_ctlmsff_ctl_macro__width_1:mb_enable_reg , spc_mb0_ctlmsff_ctl_macro__width_2:config_reg , spc_mb0_ctlmsff_ctl_macro__width_1:loop_again_reg , spc_mb0_ctlmsff_ctl_macro__width_4:cambist_delay_reg , spc_mb0_ctlmsff_ctl_macro__width_27:cam_cntl_reg , spc_mb0_ctlmsff_ctl_macro__width_1:cam_shift_reg , spc_mb0_ctlmsff_ctl_macro__width_1:cam_en_reg , spc_mb0_ctlmsff_ctl_macro__width_3:stb_hit_cmp_delay , spc_mb0_ctlmsff_ctl_macro__width_3:stb_hit_cmp_mhit_l_delay , spc_mb0_ctlmsff_ctl_macro__width_3:exp_stb_cam_hit_delay , spc_mb0_ctlmsff_ctl_macro__width_9:exp_stb_hit_ptr_delay , spc_mb0_ctlmsff_ctl_macro__width_3:exp_stb_mhit_delay , spc_mb0_ctlmsff_ctl_macro__width_3:exp_stb_ld_partial_raw_delay , spc_mb0_ctlmsff_ctl_macro__width_4:cam_array_0_delay , spc_mb0_ctlmsff_ctl_macro__width_5:cam_array_1_delay , spc_mb0_ctlmsff_ctl_macro__width_3:cam_array_2_delay , spc_mb0_ctlmsff_ctl_macro__width_6:cam_hit_cmp_delay , spc_mb0_ctlmsff_ctl_macro__width_5:data_cmp_delay , spc_mb0_ctlmsff_ctl_macro__width_5:cam_valid_cmp_delay , spc_mb0_ctlmsff_ctl_macro__width_5:cam_used_cmp_delay , spc_mb0_ctlmsff_ctl_macro__width_5:exp_data_cmp_delay , spc_mb0_ctlmsff_ctl_macro__width_5:exp_valid_delay , spc_mb0_ctlmsff_ctl_macro__width_5:exp_used_delay , spc_mb0_ctlmsff_ctl_macro__width_6:tlb_cntx0_cmp_delay , spc_mb0_ctlmsff_ctl_macro__width_6:exp_cam_hit_delay , spc_mb0_ctlmsff_ctl_macro__width_6:exp_cntx0_hit_delay , spc_mb0_ctlmsff_ctl_macro__width_6:exp_mhit_delay , spc_mb0_ctlmsff_ctl_macro__width_13:tlb_cam_intf_out , spc_mb0_ctlmsff_ctl_macro__width_28:cntl_reg , spc_mb0_ctlmsff_ctl_macro__width_4:ctest_reg , spc_mb0_ctlmsff_ctl_macro__width_3:cseq_reg , spc_mb0_ctlmsff_ctl_macro__width_4:array_sel_reg , spc_mb0_ctlmsff_ctl_macro__width_3:cmp_sel_reg , spc_mb0_ctlmsff_ctl_macro__width_4:marche_element_reg , spc_mb0_ctlmsff_ctl_macro__width_1:msb_latch , spc_mb0_ctlmsff_ctl_macro__width_1:run3_transition_reg , spc_mb0_ctlmsff_ctl_macro__width_5:done_delay_reg , spc_mb0_ctlmsff_ctl_macro__width_15:fail_reg , spc_mb0_ctlmsff_ctl_macro__width_1:out_mb_tcu_done_reg , spc_mb0_ctlmsff_ctl_macro__width_1:out_mb_tcu_fail_reg , spc_mb0_ctlmsff_ctl_macro__width_3:out_cmp_sel_reg , spc_mb0_ctlmsff_ctl_macro__width_1:out_run_mb_arrays_reg , spc_mb0_ctlmsff_ctl_macro__width_8:out_data_mb_arrays_reg , spc_mb0_ctlmsff_ctl_macro__width_9:out_addr_mb_arrays_reg , spc_mb0_ctlmsff_ctl_macro__width_12:out_wr_mb_arrays_reg , spc_mb0_ctlmsff_ctl_macro__width_12:out_rd_mb_arrays_reg , spc_mb0_ctlmsff_ctl_macro__width_3:merged_fail , spc_mb0_ctlmsff_ctl_macro__width_3:merged_done , spc_mb0_ctlspare_ctl_macro__num_6:spares 
Instantiated by:spc:mb0 
 spc_mb0_ctll1clkhdr_ctl_macro
File:spc_mb0_ctl.v
Instantiates:cl_sc1_l1hdr_8x:c_0 
Instantiated by:spc_mb0_ctl:clkgen , spc_mb0_ctl:clkgen_pm1 
 spc_mb0_ctlmsff_ctl_macro__width_1
File:spc_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb0_ctl:user_addr_mode_reg , spc_mb0_ctl:user_data_mode_reg , spc_mb0_ctl:user_cmpselinc_hold_reg , spc_mb0_ctl:user_loop_mode_reg , spc_mb0_ctl:ten_n_mode_reg , spc_mb0_ctl:user_cam_mode_reg , spc_mb0_ctl:user_bisi_wr_mode_reg , spc_mb0_ctl:user_bisi_rd_mode_reg , spc_mb0_ctl:mb_enable_reg , spc_mb0_ctl:loop_again_reg , spc_mb0_ctl:cam_shift_reg , spc_mb0_ctl:cam_en_reg , spc_mb0_ctl:msb_latch , spc_mb0_ctl:run3_transition_reg , spc_mb0_ctl:out_mb_tcu_done_reg , spc_mb0_ctl:out_mb_tcu_fail_reg , spc_mb0_ctl:out_run_mb_arrays_reg 
 spc_mb0_ctlmsff_ctl_macro__width_12
File:spc_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb0_ctl:out_wr_mb_arrays_reg , spc_mb0_ctl:out_rd_mb_arrays_reg 
 spc_mb0_ctlmsff_ctl_macro__width_13
File:spc_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb0_ctl:tlb_cam_intf_out 
 spc_mb0_ctlmsff_ctl_macro__width_15
File:spc_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb0_ctl:fail_reg 
 spc_mb0_ctlmsff_ctl_macro__width_2
File:spc_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb0_ctl:user_cam_select_reg , spc_mb0_ctl:input_signals_reg , spc_mb0_ctl:config_reg 
 spc_mb0_ctlmsff_ctl_macro__width_27
File:spc_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb0_ctl:cam_cntl_reg 
 spc_mb0_ctlmsff_ctl_macro__width_28
File:spc_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb0_ctl:cntl_reg 
 spc_mb0_ctlmsff_ctl_macro__width_3
File:spc_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb0_ctl:pmen , spc_mb0_ctl:user_cmpsel_reg , spc_mb0_ctl:stb_hit_cmp_delay , spc_mb0_ctl:stb_hit_cmp_mhit_l_delay , spc_mb0_ctl:exp_stb_cam_hit_delay , spc_mb0_ctl:exp_stb_mhit_delay , spc_mb0_ctl:exp_stb_ld_partial_raw_delay , spc_mb0_ctl:cam_array_2_delay , spc_mb0_ctl:cseq_reg , spc_mb0_ctl:cmp_sel_reg , spc_mb0_ctl:out_cmp_sel_reg , spc_mb0_ctl:merged_fail , spc_mb0_ctl:merged_done 
 spc_mb0_ctlmsff_ctl_macro__width_4
File:spc_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb0_ctl:array_usr_reg , spc_mb0_ctl:user_cam_test_select_reg , spc_mb0_ctl:cambist_delay_reg , spc_mb0_ctl:cam_array_0_delay , spc_mb0_ctl:ctest_reg , spc_mb0_ctl:array_sel_reg , spc_mb0_ctl:marche_element_reg 
 spc_mb0_ctlmsff_ctl_macro__width_5
File:spc_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb0_ctl:cam_array_1_delay , spc_mb0_ctl:data_cmp_delay , spc_mb0_ctl:cam_valid_cmp_delay , spc_mb0_ctl:cam_used_cmp_delay , spc_mb0_ctl:exp_data_cmp_delay , spc_mb0_ctl:exp_valid_delay , spc_mb0_ctl:exp_used_delay , spc_mb0_ctl:done_delay_reg 
 spc_mb0_ctlmsff_ctl_macro__width_6
File:spc_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb0_ctl:cam_hit_cmp_delay , spc_mb0_ctl:tlb_cntx0_cmp_delay , spc_mb0_ctl:exp_cam_hit_delay , spc_mb0_ctl:exp_cntx0_hit_delay , spc_mb0_ctl:exp_mhit_delay 
 spc_mb0_ctlmsff_ctl_macro__width_8
File:spc_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb0_ctl:user_data_reg , spc_mb0_ctl:out_data_mb_arrays_reg 
 spc_mb0_ctlmsff_ctl_macro__width_9
File:spc_mb0_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb0_ctl:user_start_addr_reg , spc_mb0_ctl:user_stop_addr_reg , spc_mb0_ctl:user_incr_addr_reg , spc_mb0_ctl:exp_stb_hit_ptr_delay , spc_mb0_ctl:out_addr_mb_arrays_reg 
 spc_mb0_ctlspare_ctl_macro__num_6
File:spc_mb0_ctl.v
Instantiates:cl_sc1_msff_8x:spare0_flop , cl_u1_buf_32x:spare0_buf_32x , cl_u1_nand3_8x:spare0_nand3_8x , cl_u1_inv_8x:spare0_inv_8x , cl_u1_aoi22_4x:spare0_aoi22_4x , cl_u1_buf_8x:spare0_buf_8x , cl_u1_oai22_4x:spare0_oai22_4x , cl_u1_inv_16x:spare0_inv_16x , cl_u1_nand2_16x:spare0_nand2_16x , cl_u1_nor3_4x:spare0_nor3_4x , cl_u1_nand2_8x:spare0_nand2_8x , cl_u1_buf_16x:spare0_buf_16x , cl_u1_nor2_16x:spare0_nor2_16x , cl_u1_inv_32x:spare0_inv_32x , cl_sc1_msff_8x:spare1_flop , cl_u1_buf_32x:spare1_buf_32x , cl_u1_nand3_8x:spare1_nand3_8x , cl_u1_inv_8x:spare1_inv_8x , cl_u1_aoi22_4x:spare1_aoi22_4x , cl_u1_buf_8x:spare1_buf_8x , cl_u1_oai22_4x:spare1_oai22_4x , cl_u1_inv_16x:spare1_inv_16x , cl_u1_nand2_16x:spare1_nand2_16x , cl_u1_nor3_4x:spare1_nor3_4x , cl_u1_nand2_8x:spare1_nand2_8x , cl_u1_buf_16x:spare1_buf_16x , cl_u1_nor2_16x:spare1_nor2_16x , cl_u1_inv_32x:spare1_inv_32x , cl_sc1_msff_8x:spare2_flop , cl_u1_buf_32x:spare2_buf_32x , cl_u1_nand3_8x:spare2_nand3_8x , cl_u1_inv_8x:spare2_inv_8x , cl_u1_aoi22_4x:spare2_aoi22_4x , cl_u1_buf_8x:spare2_buf_8x , cl_u1_oai22_4x:spare2_oai22_4x , cl_u1_inv_16x:spare2_inv_16x , cl_u1_nand2_16x:spare2_nand2_16x , cl_u1_nor3_4x:spare2_nor3_4x , cl_u1_nand2_8x:spare2_nand2_8x , cl_u1_buf_16x:spare2_buf_16x , cl_u1_nor2_16x:spare2_nor2_16x , cl_u1_inv_32x:spare2_inv_32x , cl_sc1_msff_8x:spare3_flop , cl_u1_buf_32x:spare3_buf_32x , cl_u1_nand3_8x:spare3_nand3_8x , cl_u1_inv_8x:spare3_inv_8x , cl_u1_aoi22_4x:spare3_aoi22_4x , cl_u1_buf_8x:spare3_buf_8x , cl_u1_oai22_4x:spare3_oai22_4x , cl_u1_inv_16x:spare3_inv_16x , cl_u1_nand2_16x:spare3_nand2_16x , cl_u1_nor3_4x:spare3_nor3_4x , cl_u1_nand2_8x:spare3_nand2_8x , cl_u1_buf_16x:spare3_buf_16x , cl_u1_nor2_16x:spare3_nor2_16x , cl_u1_inv_32x:spare3_inv_32x , cl_sc1_msff_8x:spare4_flop , cl_u1_buf_32x:spare4_buf_32x , cl_u1_nand3_8x:spare4_nand3_8x , cl_u1_inv_8x:spare4_inv_8x , cl_u1_aoi22_4x:spare4_aoi22_4x , cl_u1_buf_8x:spare4_buf_8x , cl_u1_oai22_4x:spare4_oai22_4x , cl_u1_inv_16x:spare4_inv_16x , cl_u1_nand2_16x:spare4_nand2_16x , cl_u1_nor3_4x:spare4_nor3_4x , cl_u1_nand2_8x:spare4_nand2_8x , cl_u1_buf_16x:spare4_buf_16x , cl_u1_nor2_16x:spare4_nor2_16x , cl_u1_inv_32x:spare4_inv_32x , cl_sc1_msff_8x:spare5_flop , cl_u1_buf_32x:spare5_buf_32x , cl_u1_nand3_8x:spare5_nand3_8x , cl_u1_inv_8x:spare5_inv_8x , cl_u1_aoi22_4x:spare5_aoi22_4x , cl_u1_buf_8x:spare5_buf_8x , cl_u1_oai22_4x:spare5_oai22_4x , cl_u1_inv_16x:spare5_inv_16x , cl_u1_nand2_16x:spare5_nand2_16x , cl_u1_nor3_4x:spare5_nor3_4x , cl_u1_nand2_8x:spare5_nand2_8x , cl_u1_buf_16x:spare5_buf_16x , cl_u1_nor2_16x:spare5_nor2_16x , cl_u1_inv_32x:spare5_inv_32x 
Instantiated by:spc_mb0_ctl:spares 
 spc_mb1_ctl
File:spc_mb1_ctl.v
Instantiates:spc_mb1_ctll1clkhdr_ctl_macro:clkgen , spc_mb1_ctlmsff_ctl_macro__width_3:pmen , spc_mb1_ctll1clkhdr_ctl_macro:clkgen_pm1 , spc_mb1_ctlmsff_ctl_macro__width_2:input_signals_reg , spc_mb1_ctlmsff_ctl_macro__width_1:mb_enable_reg , spc_mb1_ctlmsff_ctl_macro__width_2:config_reg , spc_mb1_ctlmsff_ctl_macro__width_1:loop_again_reg , spc_mb1_ctlmsff_ctl_macro__width_4:array_usr_reg , spc_mb1_ctlmsff_ctl_macro__width_1:user_addr_mode_reg , spc_mb1_ctlmsff_ctl_macro__width_5:user_start_addr_reg , spc_mb1_ctlmsff_ctl_macro__width_5:user_stop_addr_reg , spc_mb1_ctlmsff_ctl_macro__width_5:user_incr_addr_reg , spc_mb1_ctlmsff_ctl_macro__width_1:user_data_mode_reg , spc_mb1_ctlmsff_ctl_macro__width_8:user_data_reg , spc_mb1_ctlmsff_ctl_macro__width_1:user_cmpselinc_hold_reg , spc_mb1_ctlmsff_ctl_macro__width_3:user_cmpsel_reg , spc_mb1_ctlmsff_ctl_macro__width_1:user_loop_mode_reg , spc_mb1_ctlmsff_ctl_macro__width_1:ten_n_mode_reg , spc_mb1_ctlmsff_ctl_macro__width_1:user_bisi_wr_mode_reg , spc_mb1_ctlmsff_ctl_macro__width_1:user_bisi_rd_mode_reg , spc_mb1_ctlmsff_ctl_macro__width_24:cntl_reg , spc_mb1_ctlmsff_ctl_macro__width_4:array_sel_reg , spc_mb1_ctlmsff_ctl_macro__width_3:cmp_sel_reg , spc_mb1_ctlmsff_ctl_macro__width_4:marche_element_reg , spc_mb1_ctlmsff_ctl_macro__width_1:msb_latch , spc_mb1_ctlmsff_ctl_macro__width_1:run3_transition_reg , spc_mb1_ctlmsff_ctl_macro__width_5:done_delay_reg , spc_mb1_ctlmsff_ctl_macro__width_7:fail_reg , spc_mb1_ctlmsff_ctl_macro__width_1:out_mb_tcu_done_reg , spc_mb1_ctlmsff_ctl_macro__width_1:out_mb_tcu_fail_reg , spc_mb1_ctlmsff_ctl_macro__width_5:out_cmp_sel_reg , spc_mb1_ctlmsff_ctl_macro__width_1:out_run_mb_arrays_reg , spc_mb1_ctlmsff_ctl_macro__width_8:out_data_mb_arrays_reg , spc_mb1_ctlmsff_ctl_macro__width_5:out_addr_mb_arrays_reg , spc_mb1_ctlmsff_ctl_macro__width_7:out_wr_mb_arrays_reg , spc_mb1_ctlmsff_ctl_macro__width_7:out_rd_mb_arrays_reg , spc_mb1_ctlspare_ctl_macro__num_2:spares 
Instantiated by:spc:mb1 
 spc_mb1_ctll1clkhdr_ctl_macro
File:spc_mb1_ctl.v
Instantiates:cl_sc1_l1hdr_8x:c_0 
Instantiated by:spc_mb1_ctl:clkgen , spc_mb1_ctl:clkgen_pm1 
 spc_mb1_ctlmsff_ctl_macro__width_1
File:spc_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb1_ctl:mb_enable_reg , spc_mb1_ctl:loop_again_reg , spc_mb1_ctl:user_addr_mode_reg , spc_mb1_ctl:user_data_mode_reg , spc_mb1_ctl:user_cmpselinc_hold_reg , spc_mb1_ctl:user_loop_mode_reg , spc_mb1_ctl:ten_n_mode_reg , spc_mb1_ctl:user_bisi_wr_mode_reg , spc_mb1_ctl:user_bisi_rd_mode_reg , spc_mb1_ctl:msb_latch , spc_mb1_ctl:run3_transition_reg , spc_mb1_ctl:out_mb_tcu_done_reg , spc_mb1_ctl:out_mb_tcu_fail_reg , spc_mb1_ctl:out_run_mb_arrays_reg 
 spc_mb1_ctlmsff_ctl_macro__width_2
File:spc_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb1_ctl:input_signals_reg , spc_mb1_ctl:config_reg 
 spc_mb1_ctlmsff_ctl_macro__width_24
File:spc_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb1_ctl:cntl_reg 
 spc_mb1_ctlmsff_ctl_macro__width_3
File:spc_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb1_ctl:pmen , spc_mb1_ctl:user_cmpsel_reg , spc_mb1_ctl:cmp_sel_reg 
 spc_mb1_ctlmsff_ctl_macro__width_4
File:spc_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb1_ctl:array_usr_reg , spc_mb1_ctl:array_sel_reg , spc_mb1_ctl:marche_element_reg 
 spc_mb1_ctlmsff_ctl_macro__width_5
File:spc_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb1_ctl:user_start_addr_reg , spc_mb1_ctl:user_stop_addr_reg , spc_mb1_ctl:user_incr_addr_reg , spc_mb1_ctl:done_delay_reg , spc_mb1_ctl:out_cmp_sel_reg , spc_mb1_ctl:out_addr_mb_arrays_reg 
 spc_mb1_ctlmsff_ctl_macro__width_7
File:spc_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb1_ctl:fail_reg , spc_mb1_ctl:out_wr_mb_arrays_reg , spc_mb1_ctl:out_rd_mb_arrays_reg 
 spc_mb1_ctlmsff_ctl_macro__width_8
File:spc_mb1_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb1_ctl:user_data_reg , spc_mb1_ctl:out_data_mb_arrays_reg 
 spc_mb1_ctlspare_ctl_macro__num_2
File:spc_mb1_ctl.v
Instantiates:cl_sc1_msff_8x:spare0_flop , cl_u1_buf_32x:spare0_buf_32x , cl_u1_nand3_8x:spare0_nand3_8x , cl_u1_inv_8x:spare0_inv_8x , cl_u1_aoi22_4x:spare0_aoi22_4x , cl_u1_buf_8x:spare0_buf_8x , cl_u1_oai22_4x:spare0_oai22_4x , cl_u1_inv_16x:spare0_inv_16x , cl_u1_nand2_16x:spare0_nand2_16x , cl_u1_nor3_4x:spare0_nor3_4x , cl_u1_nand2_8x:spare0_nand2_8x , cl_u1_buf_16x:spare0_buf_16x , cl_u1_nor2_16x:spare0_nor2_16x , cl_u1_inv_32x:spare0_inv_32x , cl_sc1_msff_8x:spare1_flop , cl_u1_buf_32x:spare1_buf_32x , cl_u1_nand3_8x:spare1_nand3_8x , cl_u1_inv_8x:spare1_inv_8x , cl_u1_aoi22_4x:spare1_aoi22_4x , cl_u1_buf_8x:spare1_buf_8x , cl_u1_oai22_4x:spare1_oai22_4x , cl_u1_inv_16x:spare1_inv_16x , cl_u1_nand2_16x:spare1_nand2_16x , cl_u1_nor3_4x:spare1_nor3_4x , cl_u1_nand2_8x:spare1_nand2_8x , cl_u1_buf_16x:spare1_buf_16x , cl_u1_nor2_16x:spare1_nor2_16x , cl_u1_inv_32x:spare1_inv_32x 
Instantiated by:spc_mb1_ctl:spares 
 spc_mb2_ctl
File:spc_mb2_ctl.v
Instantiates:spc_mb2_ctll1clkhdr_ctl_macro:clkgen , spc_mb2_ctlmsff_ctl_macro__width_3:pmen , spc_mb2_ctll1clkhdr_ctl_macro:clkgen_pm1 , spc_mb2_ctlmsff_ctl_macro__width_2:input_signals_reg , spc_mb2_ctlmsff_ctl_macro__width_1:mb_enable_reg , spc_mb2_ctlmsff_ctl_macro__width_2:config_reg , spc_mb2_ctlmsff_ctl_macro__width_1:loop_again_reg , spc_mb2_ctlmsff_ctl_macro__width_4:array_usr_reg , spc_mb2_ctlmsff_ctl_macro__width_1:user_addr_mode_reg , spc_mb2_ctlmsff_ctl_macro__width_10:user_start_addr_reg , spc_mb2_ctlmsff_ctl_macro__width_10:user_stop_addr_reg , spc_mb2_ctlmsff_ctl_macro__width_10:user_incr_addr_reg , spc_mb2_ctlmsff_ctl_macro__width_1:user_data_mode_reg , spc_mb2_ctlmsff_ctl_macro__width_8:user_data_reg , spc_mb2_ctlmsff_ctl_macro__width_1:user_cmpselinc_hold_reg , spc_mb2_ctlmsff_ctl_macro__width_3:user_cmpsel_reg , spc_mb2_ctlmsff_ctl_macro__width_1:user_loop_mode_reg , spc_mb2_ctlmsff_ctl_macro__width_1:ten_n_mode_reg , spc_mb2_ctlmsff_ctl_macro__width_1:user_bisi_wr_mode_reg , spc_mb2_ctlmsff_ctl_macro__width_1:user_bisi_rd_mode_reg , spc_mb2_ctlmsff_ctl_macro__width_3:cmp_sel_reg , spc_mb2_ctlmsff_ctl_macro__width_29:cntl_reg , spc_mb2_ctlmsff_ctl_macro__width_4:array_sel_reg , spc_mb2_ctlmsff_ctl_macro__width_4:marche_element_reg , spc_mb2_ctlmsff_ctl_macro__width_6:fail_reg , spc_mb2_ctlmsff_ctl_macro__width_1:msb_latch , spc_mb2_ctlmsff_ctl_macro__width_1:run3_transition_reg , spc_mb2_ctlmsff_ctl_macro__width_5:done_delay_reg , spc_mb2_ctlmsff_ctl_macro__width_1:out_run_mb_arrays_reg , spc_mb2_ctlmsff_ctl_macro__width_8:out_data_mb_arrays_reg , spc_mb2_ctlmsff_ctl_macro__width_16:out_addr_mb_arrays_reg , spc_mb2_ctlmsff_ctl_macro__width_5:out_wr_mb_arrays_reg , spc_mb2_ctlmsff_ctl_macro__width_5:out_rd_mb_arrays_reg , spc_mb2_ctlmsff_ctl_macro__width_1:out_mb_tcu_done_reg , spc_mb2_ctlmsff_ctl_macro__width_1:out_mb_tcu_fail_reg , spc_mb2_ctlspare_ctl_macro__num_3:spares , spc_mb2_ctlmsff_ctl_macro__width_4:i_delay_4th , spc_mb2_ctlmsff_ctl_macro__width_22:delayed_cmp_rd_data_reg , spc_mb2_ctlmsff_ctl_macro__width_2:out_save_restore_mb_arrays_reg 
Instantiated by:spc:mb2 
 spc_mb2_ctll1clkhdr_ctl_macro
File:spc_mb2_ctl.v
Instantiates:cl_sc1_l1hdr_8x:c_0 
Instantiated by:spc_mb2_ctl:clkgen , spc_mb2_ctl:clkgen_pm1 
 spc_mb2_ctlmsff_ctl_macro__width_1
File:spc_mb2_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb2_ctl:mb_enable_reg , spc_mb2_ctl:loop_again_reg , spc_mb2_ctl:user_addr_mode_reg , spc_mb2_ctl:user_data_mode_reg , spc_mb2_ctl:user_cmpselinc_hold_reg , spc_mb2_ctl:user_loop_mode_reg , spc_mb2_ctl:ten_n_mode_reg , spc_mb2_ctl:user_bisi_wr_mode_reg , spc_mb2_ctl:user_bisi_rd_mode_reg , spc_mb2_ctl:msb_latch , spc_mb2_ctl:run3_transition_reg , spc_mb2_ctl:out_run_mb_arrays_reg , spc_mb2_ctl:out_mb_tcu_done_reg , spc_mb2_ctl:out_mb_tcu_fail_reg 
 spc_mb2_ctlmsff_ctl_macro__width_10
File:spc_mb2_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb2_ctl:user_start_addr_reg , spc_mb2_ctl:user_stop_addr_reg , spc_mb2_ctl:user_incr_addr_reg 
 spc_mb2_ctlmsff_ctl_macro__width_16
File:spc_mb2_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb2_ctl:out_addr_mb_arrays_reg 
 spc_mb2_ctlmsff_ctl_macro__width_2
File:spc_mb2_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb2_ctl:input_signals_reg , spc_mb2_ctl:config_reg , spc_mb2_ctl:out_save_restore_mb_arrays_reg 
 spc_mb2_ctlmsff_ctl_macro__width_22
File:spc_mb2_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb2_ctl:delayed_cmp_rd_data_reg 
 spc_mb2_ctlmsff_ctl_macro__width_29
File:spc_mb2_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb2_ctl:cntl_reg 
 spc_mb2_ctlmsff_ctl_macro__width_3
File:spc_mb2_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb2_ctl:pmen , spc_mb2_ctl:user_cmpsel_reg , spc_mb2_ctl:cmp_sel_reg 
 spc_mb2_ctlmsff_ctl_macro__width_4
File:spc_mb2_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb2_ctl:array_usr_reg , spc_mb2_ctl:array_sel_reg , spc_mb2_ctl:marche_element_reg , spc_mb2_ctl:i_delay_4th 
 spc_mb2_ctlmsff_ctl_macro__width_5
File:spc_mb2_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb2_ctl:done_delay_reg , spc_mb2_ctl:out_wr_mb_arrays_reg , spc_mb2_ctl:out_rd_mb_arrays_reg 
 spc_mb2_ctlmsff_ctl_macro__width_6
File:spc_mb2_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb2_ctl:fail_reg 
 spc_mb2_ctlmsff_ctl_macro__width_8
File:spc_mb2_ctl.v
Instantiates:dff:d0_0 
Instantiated by:spc_mb2_ctl:user_data_reg , spc_mb2_ctl:out_data_mb_arrays_reg 
 spc_mb2_ctlspare_ctl_macro__num_3
File:spc_mb2_ctl.v
Instantiates:cl_sc1_msff_8x:spare0_flop , cl_u1_buf_32x:spare0_buf_32x , cl_u1_nand3_8x:spare0_nand3_8x , cl_u1_inv_8x:spare0_inv_8x , cl_u1_aoi22_4x:spare0_aoi22_4x , cl_u1_buf_8x:spare0_buf_8x , cl_u1_oai22_4x:spare0_oai22_4x , cl_u1_inv_16x:spare0_inv_16x , cl_u1_nand2_16x:spare0_nand2_16x , cl_u1_nor3_4x:spare0_nor3_4x , cl_u1_nand2_8x:spare0_nand2_8x , cl_u1_buf_16x:spare0_buf_16x , cl_u1_nor2_16x:spare0_nor2_16x , cl_u1_inv_32x:spare0_inv_32x , cl_sc1_msff_8x:spare1_flop , cl_u1_buf_32x:spare1_buf_32x , cl_u1_nand3_8x:spare1_nand3_8x , cl_u1_inv_8x:spare1_inv_8x , cl_u1_aoi22_4x:spare1_aoi22_4x , cl_u1_buf_8x:spare1_buf_8x , cl_u1_oai22_4x:spare1_oai22_4x , cl_u1_inv_16x:spare1_inv_16x , cl_u1_nand2_16x:spare1_nand2_16x , cl_u1_nor3_4x:spare1_nor3_4x , cl_u1_nand2_8x:spare1_nand2_8x , cl_u1_buf_16x:spare1_buf_16x , cl_u1_nor2_16x:spare1_nor2_16x , cl_u1_inv_32x:spare1_inv_32x , cl_sc1_msff_8x:spare2_flop , cl_u1_buf_32x:spare2_buf_32x , cl_u1_nand3_8x:spare2_nand3_8x , cl_u1_inv_8x:spare2_inv_8x , cl_u1_aoi22_4x:spare2_aoi22_4x , cl_u1_buf_8x:spare2_buf_8x , cl_u1_oai22_4x:spare2_oai22_4x , cl_u1_inv_16x:spare2_inv_16x , cl_u1_nand2_16x:spare2_nand2_16x , cl_u1_nor3_4x:spare2_nor3_4x , cl_u1_nand2_8x:spare2_nand2_8x , cl_u1_buf_16x:spare2_buf_16x , cl_u1_nor2_16x:spare2_nor2_16x , cl_u1_inv_32x:spare2_inv_32x 
Instantiated by:spc_mb2_ctl:spares 
 spc_msf0_dp
File:spc_msf0_dp.v
Instantiates:spc_msf0_dpmsff_macro__stack_10r__width_8:bank0_lat , spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_8:bank0_rep , spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_11:bank1_rep1 , spc_msf0_dpmsff_macro__stack_8r__width_8:bank1_lat , spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_1:bank2_rep1 , spc_msf0_dpmsff_macro__stack_8r__width_3:bank2_lat , spc_msf0_dpbuff_macro__dbuff_16x__rep_1__stack_none__width_5:bank3_rep0 , spc_msf0_dpinv_macro__width_1:bank3_inv , spc_msf0_dpand_macro__width_5:bank3_and , spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_19:bank3_rep1 , spc_msf0_dpmsff_macro__stack_10r__width_10:bank3_lat , spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_5:bank4_rep1 , spc_msf0_dpmsff_macro__stack_8r__width_4:bank4_lat , spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_4:bank5_rep1 , spc_msf0_dpmsff_macro__stack_8r__width_4:bank5_lat 
Instantiated by:spc:msf0 
 spc_msf0_dpand_macro__width_5
File:spc_msf0_dp.v
Instantiates:and2:d0_0 
Instantiated by:spc_msf0_dp:bank3_and 
 spc_msf0_dpbuff_macro__dbuff_16x__rep_1__stack_none__width_5
File:spc_msf0_dp.v
Instantiates:buff:d0_0 
Instantiated by:spc_msf0_dp:bank3_rep0 
 spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_1
File:spc_msf0_dp.v
Instantiates:buff:d0_0 
Instantiated by:spc_msf0_dp:bank2_rep1 
 spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_11
File:spc_msf0_dp.v
Instantiates:buff:d0_0 
Instantiated by:spc_msf0_dp:bank1_rep1 
 spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_19
File:spc_msf0_dp.v
Instantiates:buff:d0_0 
Instantiated by:spc_msf0_dp:bank3_rep1 
 spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_4
File:spc_msf0_dp.v
Instantiates:buff:d0_0 
Instantiated by:spc_msf0_dp:bank5_rep1 
 spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_5
File:spc_msf0_dp.v
Instantiates:buff:d0_0 
Instantiated by:spc_msf0_dp:bank4_rep1 
 spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_8
File:spc_msf0_dp.v
Instantiates:buff:d0_0 
Instantiated by:spc_msf0_dp:bank0_rep 
 spc_msf0_dpinv_macro__width_1
File:spc_msf0_dp.v
Instantiates:inv:d0_0 
Instantiated by:spc_msf0_dp:bank3_inv 
 spc_msf0_dpmsff_macro__stack_10r__width_10
File:spc_msf0_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:spc_msf0_dp:bank3_lat 
 spc_msf0_dpmsff_macro__stack_10r__width_8
File:spc_msf0_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:spc_msf0_dp:bank0_lat 
 spc_msf0_dpmsff_macro__stack_8r__width_3
File:spc_msf0_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:spc_msf0_dp:bank2_lat 
 spc_msf0_dpmsff_macro__stack_8r__width_4
File:spc_msf0_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:spc_msf0_dp:bank4_lat , spc_msf0_dp:bank5_lat 
 spc_msf0_dpmsff_macro__stack_8r__width_8
File:spc_msf0_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:spc_msf0_dp:bank1_lat 
 spc_msf1_dp
File:spc_msf1_dp.v
Instantiates:spc_msf1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_1:chip_io_rep0 , spc_msf1_dpmsff_macro__stack_8r__width_3:bank0_lat 
Instantiated by:spc:msf1 
 spc_msf1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_1
File:spc_msf1_dp.v
Instantiates:buff:d0_0 
Instantiated by:spc_msf1_dp:chip_io_rep0 
 spc_msf1_dpmsff_macro__stack_8r__width_3
File:spc_msf1_dp.v
Instantiates:cl_dp1_l1hdr_8x:c0_0 , dff:d0_0 
Instantiated by:spc_msf1_dp:bank0_lat 
 spc_rep1_dp
File:spc_rep1_dp.v
Instantiates:spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__vertical_1__width_37:chip_io_rep0 , spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_1:spu_grant_rep0 , spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_5:hf_tl_rep0 , spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_5:hf_tr_rep0 , spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_5:hf_br_rep0 , spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_5:hf_bl_rep0 , spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38:ftu_instr_0_rep0 , spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38:ftu_instr_0_rep1 , spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38:ftu_instr_0_rep2 , spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38:ftu_instr_0_rep3 , spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38:ftu_instr_1_rep0 , spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38:ftu_instr_1_rep1 , spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38:ftu_instr_1_rep2 , spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38:ftu_instr_1_rep3 , spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38:ftu_instr_2_rep0 , spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38:ftu_instr_2_rep1 , spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38:ftu_instr_2_rep2 , spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38:ftu_instr_2_rep3 , spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38:ftu_instr_3_rep0 , spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38:ftu_instr_3_rep1 , spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38:ftu_instr_3_rep2 , spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38:ftu_instr_3_rep3 , spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_64c__width_48:i_exu_address0_e_rep0 , spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_50c__width_48:i_exu_address0_e_rep01 , spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_64c__width_48:i_exu_address1_e_rep0 , spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_50c__width_48:i_exu_address1_e_rep01 , spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__top_lsb__vertical_1__width_32:i_fgu_exu_result_fx5_rep0a , spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__top_lsb__vertical_1__width_32:i_fgu_exu_result_fx5_rep0b , spc_rep1_dpbuff_macro__dbuff_16x__rep_1__stack_none__top_lsb__vertical_1__width_32:i_fgu_exu_result_fx5_rep1a , spc_rep1_dpbuff_macro__dbuff_16x__rep_1__stack_none__top_lsb__vertical_1__width_32:i_fgu_exu_result_fx5_rep1b , spc_rep1_dpbuff_macro__dbuff_16x__rep_1__stack_72c__width_64:i_lsu_exu_ld_data_rep00 , spc_rep1_dpbuff_macro__dbuff_16x__rep_1__stack_72c__width_64:i_lsu_exu_ld_data_rep01 , spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_2:i_fgu_ecc_fx2_rep0 , spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__vertical_1__width_2:i_fgu_ecc_fx2_rep1 
Instantiated by:spc:rep1 
 spc_rep1_dpbuff_macro__dbuff_16x__rep_1__stack_72c__width_64
File:spc_rep1_dp.v
Instantiates:buff:d0_0 
Instantiated by:spc_rep1_dp:i_lsu_exu_ld_data_rep00 , spc_rep1_dp:i_lsu_exu_ld_data_rep01 
 spc_rep1_dpbuff_macro__dbuff_16x__rep_1__stack_none__top_lsb__vertical_1__width_32
File:spc_rep1_dp.v
Instantiates:buff:d0_0 
Instantiated by:spc_rep1_dp:i_fgu_exu_result_fx5_rep1a , spc_rep1_dp:i_fgu_exu_result_fx5_rep1b 
 spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_50c__width_48
File:spc_rep1_dp.v
Instantiates:buff:d0_0 
Instantiated by:spc_rep1_dp:i_exu_address0_e_rep01 , spc_rep1_dp:i_exu_address1_e_rep01 
 spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_64c__width_48
File:spc_rep1_dp.v
Instantiates:buff:d0_0 
Instantiated by:spc_rep1_dp:i_exu_address0_e_rep0 , spc_rep1_dp:i_exu_address1_e_rep0 
 spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__top_lsb__vertical_1__width_32
File:spc_rep1_dp.v
Instantiates:buff:d0_0 
Instantiated by:spc_rep1_dp:i_fgu_exu_result_fx5_rep0a , spc_rep1_dp:i_fgu_exu_result_fx5_rep0b 
 spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__vertical_1__width_2
File:spc_rep1_dp.v
Instantiates:buff:d0_0 
Instantiated by:spc_rep1_dp:i_fgu_ecc_fx2_rep1 
 spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__vertical_1__width_37
File:spc_rep1_dp.v
Instantiates:buff:d0_0 
Instantiated by:spc_rep1_dp:chip_io_rep0 
 spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_1
File:spc_rep1_dp.v
Instantiates:buff:d0_0 
Instantiated by:spc_rep1_dp:spu_grant_rep0 
 spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_2
File:spc_rep1_dp.v
Instantiates:buff:d0_0 
Instantiated by:spc_rep1_dp:i_fgu_ecc_fx2_rep0 
 spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_5
File:spc_rep1_dp.v
Instantiates:buff:d0_0 
Instantiated by:spc_rep1_dp:hf_tl_rep0 , spc_rep1_dp:hf_tr_rep0 , spc_rep1_dp:hf_br_rep0 , spc_rep1_dp:hf_bl_rep0 
 spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38
File:spc_rep1_dp.v
Instantiates:buff:d0_0 
Instantiated by:spc_rep1_dp:ftu_instr_0_rep0 , spc_rep1_dp:ftu_instr_0_rep1 , spc_rep1_dp:ftu_instr_0_rep2 , spc_rep1_dp:ftu_instr_0_rep3 , spc_rep1_dp:ftu_instr_1_rep0 , spc_rep1_dp:ftu_instr_1_rep1 , spc_rep1_dp:ftu_instr_1_rep2 , spc_rep1_dp:ftu_instr_1_rep3 , spc_rep1_dp:ftu_instr_2_rep0 , spc_rep1_dp:ftu_instr_2_rep1 , spc_rep1_dp:ftu_instr_2_rep2 , spc_rep1_dp:ftu_instr_2_rep3 , spc_rep1_dp:ftu_instr_3_rep0 , spc_rep1_dp:ftu_instr_3_rep1 , spc_rep1_dp:ftu_instr_3_rep2 , spc_rep1_dp:ftu_instr_3_rep3 
 sphy_dpath2
File:sphy_dpath2.v
Instantiates:RegDff:xtx_code_group_reg0_RegDff , n2_txd_blatch:port0_n2_txd_blatch , xMUX_2to1:mac_esr_txd0_0_p1_xMUX_2to1 , xMUX_2to1:mac_esr_txd0_0_xMUX , xMUX_2to1:mac_esr_txd1_0_xMUX , xMUX_2to1:mac_esr_txd2_0_xMUX , xMUX_2to1:mac_esr_txd3_0_xMUX , n2_rxd_alatch:port0_n2_rxd_alatch , RegDff:odd_rx0_RegDff , RegDff:esr_mac_rxd0_0_blunt_RegDff , RegDff:esr_mac_rxd1_0_blunt_RegDff , RegDff:esr_mac_rxd2_0_blunt_RegDff , RegDff:esr_mac_rxd3_0_blunt_RegDff , RegDff:xtx_code_group_reg1_RegDff , n2_txd_blatch:port1_n2_txd_blatch , xMUX_2to1:mac_esr_txd0_1_p1_xMUX_2to1 , xMUX_2to1:mac_esr_txd0_1_xMUX , xMUX_2to1:mac_esr_txd1_1_xMUX , xMUX_2to1:mac_esr_txd2_1_xMUX , xMUX_2to1:mac_esr_txd3_1_xMUX , n2_rxd_alatch:port1_n2_rxd_alatch , RegDff:odd_rx1_RegDff , RegDff:esr_mac_rxd0_1_blunt_RegDff , RegDff:esr_mac_rxd1_1_blunt_RegDff , RegDff:esr_mac_rxd2_1_blunt_RegDff , RegDff:esr_mac_rxd3_1_blunt_RegDff 
Instantiated by:mac_2ports:sphy_dpath2 
 spu
File:spu.v
Instantiated by:spc:spu 
 SRFF
File:lib.v
Instantiated by:rx_mii_gmii:sfd_win_SRFF , esr_ctl2:serdes_rdy0_0_SRFF , esr_ctl2:serdes_rdy1_0_SRFF , esr_ctl2:serdes_rdy2_0_SRFF , esr_ctl2:serdes_rdy3_0_SRFF , esr_ctl2:serdes_rdy0_1_SRFF , esr_ctl2:serdes_rdy1_1_SRFF , esr_ctl2:serdes_rdy2_1_SRFF , esr_ctl2:serdes_rdy3_1_SRFF , pcs_link_config:timer_on_SRFF , xmac_slv:tx_led_SRFF , xmac_slv:rx_led_SRFF 
 srfifo_load
File:srfifo_load.v
Instantiates:g_cntr_5bit:srfifo_g_wr_ptr_rxclk_g_cntr_5bit , g2b_5bit:srfifo_g2b_5bit , srfifo_TBITS_memory_model:srfifo_TBITS_memory_model 
Instantiated by:rx_xmac:srfifo_load 
 srfifo_TBITS_memory_model
File:srfifo_load.v
Instantiated by:srfifo_load:srfifo_TBITS_memory_model 
 srlatch1
File:n2_l2d_sp_512kb_cust.v
Instantiated by:n2_l2d_tstmod_delay_cust:latch1_31 , n2_l2d_tstmod_delay_cust:latch1_02 
 srlatch2
File:n2_l2d_sp_512kb_cust.v
Instantiated by:n2_l2d_tstmod_delay_cust:latch2_31 , n2_l2d_tstmod_delay_cust:latch2_02 
 SRREG
File:lib.v
Instantiated by:pcs_sequence_detect:r_cfg_old_lsb , pcs_sequence_detect:r_cfg_old_msb , pcs_sequence_detect:r_cfg_new_lsb , pcs_slave:r_col_test , pcs_slave:r_shared 
 SR_FF
File:lib.v
Instantiated by:tx_mii_gmii:tx_on_mgmii_SR_FF , hs_ld_counter_X32:flag_count_SR_FF , rx_xmac:data_ready_SR_FF , SYNC_PLS:SR_FF_u1 
 stfifo_memory_model
File:txfifo_load.v
Instantiated by:txfifo_load:stfifo_memory_model 
 SYNCREG
File:lib.v
Instantiates:SYNC_CELL:PCS_SYNC_CELL 
Instantiated by:SYNCREG17:R_SYNC_0 , SYNCREG17:R_SYNC_1 , SYNCREG17:R_SYNC_2 , SYNCREG17:R_SYNC_3 , SYNCREG17:R_SYNC_4 , SYNCREG17:R_SYNC_5 , SYNCREG17:R_SYNC_6 , SYNCREG17:R_SYNC_7 , SYNCREG17:R_SYNC_8 , SYNCREG17:R_SYNC_9 , SYNCREG17:R_SYNC_10 , SYNCREG17:R_SYNC_11 , SYNCREG17:R_SYNC_12 , SYNCREG17:R_SYNC_13 , SYNCREG17:R_SYNC_14 , SYNCREG17:R_SYNC_15 , SYNCREG17:R_SYNC_16 , SYNCREG16:R_SYNC_0 , SYNCREG16:R_SYNC_1 , SYNCREG16:R_SYNC_2 , SYNCREG16:R_SYNC_3 , SYNCREG16:R_SYNC_4 , SYNCREG16:R_SYNC_5 , SYNCREG16:R_SYNC_6 , SYNCREG16:R_SYNC_7 , SYNCREG16:R_SYNC_8 , SYNCREG16:R_SYNC_9 , SYNCREG16:R_SYNC_10 , SYNCREG16:R_SYNC_11 , SYNCREG16:R_SYNC_12 , SYNCREG16:R_SYNC_13 , SYNCREG16:R_SYNC_14 , SYNCREG16:R_SYNC_15 , pcs_rx_ctrl:r_link_up_tx , pcs_rx_dpath:r_enable_rx , SYNCREG22:R_SYNC_0 , SYNCREG22:R_SYNC_1 , SYNCREG22:R_SYNC_2 , SYNCREG22:R_SYNC_3 , SYNCREG22:R_SYNC_4 , SYNCREG22:R_SYNC_5 , SYNCREG22:R_SYNC_6 , SYNCREG22:R_SYNC_7 , SYNCREG22:R_SYNC_8 , SYNCREG22:R_SYNC_9 , SYNCREG22:R_SYNC_10 , SYNCREG22:R_SYNC_11 , SYNCREG22:R_SYNC_12 , SYNCREG22:R_SYNC_13 , SYNCREG22:R_SYNC_14 , SYNCREG22:R_SYNC_15 , SYNCREG22:R_SYNC_16 , SYNCREG22:R_SYNC_17 , SYNCREG22:R_SYNC_18 , SYNCREG22:R_SYNC_19 , SYNCREG22:R_SYNC_20 , SYNCREG22:R_SYNC_21 , pcs_sequence_detect:r_reset_rx , pcs_sequence_detect:r_signal_det_rx , pcs_slave:r_link_up_pci , pcs_slave:r_rem_fault13 , pcs_slave:r_rem_fault12 , pcs_slave:r_clr_reset_t , pcs_slave:r_clr_reset_r , pcs_slave:r_ser_state1 , pcs_slave:r_ser_state0 , pcs_slave:r_lost_link , pcs_slave:r_clr_res_auto , pcs_slave:r_sigdet_optic_pci , pcs_slave:r_set_lol_from_los , pcs_slave:r_set_lol_from_c , pcs_tx_ctrl:enable_tx_SYNCREG , pcs_link_config:r_res_auto , pcs_link_config:r_loss_sync_tx , pcs_link_config:r_reset_tx , pcs_link_config:r_got_C , pcs_link_config:r_autoneg_ena_tx , pcs_link_config:r_CorData_err , pcs_link_config:r_good3_Cnack , pcs_link_config:r_good3_CorData , pcs_link_config:r_got3_config0 , pcs_link_config:r_timer_override , pcs_link_config:r_clr_lost_link , pcs_link_config:r_clr_lol_los , pcs_link_config:r_clr_lol_c , pcs_link_config:r_serdes_rdy_tx , pcs_tx_dpath:r_jitter_study1 , pcs_tx_dpath:r_jitter_study0 , SYNCREG6:R_SYNC_0 , SYNCREG6:R_SYNC_1 , SYNCREG6:R_SYNC_2 , SYNCREG6:R_SYNC_3 , SYNCREG6:R_SYNC_4 , SYNCREG6:R_SYNC_5 
 SYNCREG16
File:lib.v
Instantiates:SYNCREG:R_SYNC_0 , SYNCREG:R_SYNC_1 , SYNCREG:R_SYNC_2 , SYNCREG:R_SYNC_3 , SYNCREG:R_SYNC_4 , SYNCREG:R_SYNC_5 , SYNCREG:R_SYNC_6 , SYNCREG:R_SYNC_7 , SYNCREG:R_SYNC_8 , SYNCREG:R_SYNC_9 , SYNCREG:R_SYNC_10 , SYNCREG:R_SYNC_11 , SYNCREG:R_SYNC_12 , SYNCREG:R_SYNC_13 , SYNCREG:R_SYNC_14 , SYNCREG:R_SYNC_15 
Instantiated by:pcs_slave:r_link_part_pci 
 SYNCREG17
File:lib.v
Instantiates:SYNCREG:R_SYNC_0 , SYNCREG:R_SYNC_1 , SYNCREG:R_SYNC_2 , SYNCREG:R_SYNC_3 , SYNCREG:R_SYNC_4 , SYNCREG:R_SYNC_5 , SYNCREG:R_SYNC_6 , SYNCREG:R_SYNC_7 , SYNCREG:R_SYNC_8 , SYNCREG:R_SYNC_9 , SYNCREG:R_SYNC_10 , SYNCREG:R_SYNC_11 , SYNCREG:R_SYNC_12 , SYNCREG:R_SYNC_13 , SYNCREG:R_SYNC_14 , SYNCREG:R_SYNC_15 , SYNCREG:R_SYNC_16 
Instantiated by:pcs_slave:r_state_bits 
 SYNCREG22
File:lib.v
Instantiates:SYNCREG:R_SYNC_0 , SYNCREG:R_SYNC_1 , SYNCREG:R_SYNC_2 , SYNCREG:R_SYNC_3 , SYNCREG:R_SYNC_4 , SYNCREG:R_SYNC_5 , SYNCREG:R_SYNC_6 , SYNCREG:R_SYNC_7 , SYNCREG:R_SYNC_8 , SYNCREG:R_SYNC_9 , SYNCREG:R_SYNC_10 , SYNCREG:R_SYNC_11 , SYNCREG:R_SYNC_12 , SYNCREG:R_SYNC_13 , SYNCREG:R_SYNC_14 , SYNCREG:R_SYNC_15 , SYNCREG:R_SYNC_16 , SYNCREG:R_SYNC_17 , SYNCREG:R_SYNC_18 , SYNCREG:R_SYNC_19 , SYNCREG:R_SYNC_20 , SYNCREG:R_SYNC_21 
Instantiated by:pcs_slave:r_pkt_cnt 
 SYNCREG6
File:lib.v
Instantiates:SYNCREG:R_SYNC_0 , SYNCREG:R_SYNC_1 , SYNCREG:R_SYNC_2 , SYNCREG:R_SYNC_3 , SYNCREG:R_SYNC_4 , SYNCREG:R_SYNC_5 
Instantiated by:pcs_slave:r_link_not_up 
 SYNC_3bit
File:lib.v
Instantiates:SYNC_CELL:bit_0_SYNC_CELL , SYNC_CELL:bit_1_SYNC_CELL , SYNC_CELL:bit_2_SYNC_CELL 
 SYNC_4bit
File:lib.v
Instantiates:SYNC_CELL:bit_0_SYNC_CELL , SYNC_CELL:bit_1_SYNC_CELL , SYNC_CELL:bit_2_SYNC_CELL , SYNC_CELL:bit_3_SYNC_CELL 
 SYNC_5bit
File:lib.v
Instantiates:SYNC_CELL:bit_0_SYNC_CELL , SYNC_CELL:bit_1_SYNC_CELL , SYNC_CELL:bit_2_SYNC_CELL , SYNC_CELL:bit_3_SYNC_CELL , SYNC_CELL:bit_4_SYNC_CELL 
Instantiated by:xmac_sync:rxfifo_g_rd_ptr_sync_SYNC_5bit , xmac_sync:rxfifo_g_wr_ptr_sync_SYNC_5bit , xmac_sync:srfifo_g_wr_ptr_sync_SYNC_5bit , xmac_sync:txfifo_g_rd_ptr_sync_SYNC_5bit , xmac_sync:txfifo_g_wr_ptr_sync_SYNC_5bit , xmac_sync:stfifo_g_rd_ptr_sync_SYNC_5bit , xmac_sync:stfifo_g_wr_ptr_sync_SYNC_5bit 
 SYNC_CELL
File:lib.v
Instantiates:cl_a1_clksyncff_4x:SYNC_CELL 
Instantiated by:DIV4_CLK:hw_reset_clk_SYNC_CELL , mif:sync_MDION0_L_SYNC_CELL , mif:sync_MDION1_L_SYNC_CELL , xpcs_rx:u_sync_serdes_rdy , xpcs_rx:u_sync_xpcs_enable , xpcs_rx:u_sync_test_enable , xmac_sync:TOG_RX_BCNT_SYNC , xmac_sync:rx_data_valid_gmux_reg_clk_SYNC , xmac_sync:remote_fault_oc_sync_SYNC , xmac_sync:local_fault_oc_sync_SYNC , xmac_sync:rxfifo_full_nbclk_SYNC_CELL , xmac_sync:SYNC_RX_RESET , xmac_sync:SYNC_CLR_RX_RESET , xmac_sync:rx_enable_rxclk_SYNC , xmac_sync:lfs_disable_rxclk_SYNC , xmac_sync:hw_reset_rxnbclk_SYNC , xmac_sync:rx_reset_nbclk_SYNC , xmac_sync:rx_enable_nbclk_SYNC , xmac_sync:remote_fault_oc_txclk_SYNC , xmac_sync:local_fault_oc_txclk_SYNC , xmac_sync:PAUSED_SNC , xmac_sync:TOG_TX_BCNT_SYNC , xmac_sync:TOG_TX_FRAME_SYNC , xmac_sync:tx_data_valid_clk_SYNC , xmac_sync:TX_CLK_RESET_SYNC , xmac_sync:SYNC_CLR_TX_RESET , xmac_sync:tx_enable_txclk_SYNC , xmac_sync:tx_output_en_txclk_SYNC , xmac_sync:hw_reset_txnbclk_SYNC , xmac_sync:tx_reset_nbclk_SYNC , xmac_sync:tx_output_en_nbclk_SYNC , xpcs_sync:XPCS_CLR_SW_RESET_INT0 , xpcs_sync:XPCS_CLR_SW_RESET_INT1 , xpcs_sync:XPCS_CLR_SW_RESET , xpcs_sync:reset_txclk_CLK , xpcs_sync:reset_rxclk_CLK , xpcs_sync:XPCS_INC_RX_PKT_SYNC , xpcs_sync:XPCS_CLR_RX_PKT_SYNC , xpcs_sync:XPCS_INC_TX_PKT_SYNC , xpcs_sync:XPCS_CLR_TX_PKT_SYNC , xpcs_sync:XPCS_INC_DESKEW_ERR_SYNC , xpcs_sync:XPCS_CLR_DESKEW_ERR_SYNC , xpcs_sync:XPCS_INC_TX_FAULT_SYNC , xpcs_sync:XPCS_CLR_TX_FAULT_SYNC , xpcs_sync:XPCS_INC_RX_FAULT_SYNC , xpcs_sync:XPCS_CLR_RX_FAULT_SYNC , xpcs_sync:SYMBOL_ERR0_SYNC , xpcs_sync:CLR_SYMBOL_ERR0_SYNC , xpcs_sync:SYMBOL_ERR1_SYNC , xpcs_sync:CLR_SYMBOL_ERR1_SYNC , xpcs_sync:SYMBOL_ERR2_SYNC , xpcs_sync:CLR_SYMBOL_ERR2_SYNC , xpcs_sync:SYMBOL_ERR3_SYNC , xpcs_sync:CLR_SYMBOL_ERR3_SYNC , SYNC_5bit:bit_0_SYNC_CELL , SYNC_5bit:bit_1_SYNC_CELL , SYNC_5bit:bit_2_SYNC_CELL , SYNC_5bit:bit_3_SYNC_CELL , SYNC_5bit:bit_4_SYNC_CELL , SYNC_4bit:bit_0_SYNC_CELL , SYNC_4bit:bit_1_SYNC_CELL , SYNC_4bit:bit_2_SYNC_CELL , SYNC_4bit:bit_3_SYNC_CELL , xpcs_rxio:u_sync_rx_status_lane0 , xpcs_rxio:u_sync_rx_status_lane1 , xpcs_rxio:u_sync_rx_status_lane2 , xpcs_rxio:u_sync_rx_status_lane3 , xpcs_rxio:u_sync_core_status_lane0 , xpcs_rxio:u_sync_core_status_lane1 , xpcs_rxio:u_sync_core_status_lane2 , xpcs_rxio:u_sync_core_status_lane3 , xpcs_rxio:u_sync_link_status_core , xpcs_rxio:u_sync_signal_detect_lane0 , xpcs_rxio:u_sync_signal_detect_lane1 , xpcs_rxio:u_sync_signal_detect_lane2 , xpcs_rxio:u_sync_signal_detect_lane3 , xpcs_rxio:u_sync_reset_0 , xpcs_rxio:u_sync_reset_1 , xpcs_rxio:u_sync_reset_2 , xpcs_rxio:u_sync_reset_3 , DIV2_CLK:hw_reset_clk_SYNC_CELL , SYNC_3bit:bit_0_SYNC_CELL , SYNC_3bit:bit_1_SYNC_CELL , SYNC_3bit:bit_2_SYNC_CELL , esr_ctl2:lock_0_SYNC_CELL , esr_ctl2:lock_1_SYNC_CELL , esr_ctl2:los0_0_SYNC_CELL , esr_ctl2:los1_0_SYNC_CELL , esr_ctl2:los2_0_SYNC_CELL , esr_ctl2:los3_0_SYNC_CELL , esr_ctl2:los0_1_SYNC_CELL , esr_ctl2:los1_1_SYNC_CELL , esr_ctl2:los2_1_SYNC_CELL , esr_ctl2:los3_1_SYNC_CELL , hedwig:SYNC_CELL_ST_TX_0_0 , hedwig:SYNC_CELL_ST_TX_1_0 , hedwig:SYNC_CELL_ST_RX_0_0 , hedwig:SYNC_CELL_ST_RX_0_1 , hedwig:SYNC_CELL_ST_RX_0_2 , hedwig:SYNC_CELL_ST_RX_0_3 , hedwig:SYNC_CELL_ST_RX_1_0 , hedwig:SYNC_CELL_ST_RX_1_1 , hedwig:SYNC_CELL_ST_RX_1_2 , hedwig:SYNC_CELL_ST_RX_1_3 , hedwig:SYNC_CELL0 , hedwig:SYNC_CELL1 , hedwig:serdes_reset_0_SYNC_CELL , hedwig:serdes_reset_1_SYNC_CELL , xpcs_rxio_sync_fifo_ptr:SYNC_W_PTR_0 , xpcs_rxio_sync_fifo_ptr:SYNC_W_PTR_1 , xpcs_rxio_sync_fifo_ptr:SYNC_W_PTR_2 , xpcs_rxio_sync_fifo_ptr:SYNC_W_PTR_3 , xpcs_rxio_sync_fifo_ptr:SYNC_W_PTR_4 , xpcs_rxio_sync_fifo_ptr:SYNC_W_PTR_5 , xpcs_rxio_sync_fifo_ptr:SYNC_W_PTR_6 , xpcs_rxio_sync_fifo_ptr:SYNC_W_PTR_7 , xpcs_rxio_sync:FLUSH_SYNC , mac_pio_intf:reset_SYNC_CELL , xpcs_tx:u_sync_link_status , xpcs_tx:u_sync_test_enable , xpcs_tx:u_sync_test_pattern_sel_0 , xpcs_tx:u_sync_test_pattern_sel_1 , SYNCREG:PCS_SYNC_CELL , SYNC_PLS:go_to_des_SYNC_CELL , SYNC_PLS:back_to_src_SYNC_CELL , ipg_checker:SYNC_X2_TX_RESET 
 SYNC_FAST_5bit
File:lib.v
Instantiates:FAST_SYNC_CELL:bit_0_FAST_SYNC_CELL , FAST_SYNC_CELL:bit_1_FAST_SYNC_CELL , FAST_SYNC_CELL:bit_2_FAST_SYNC_CELL , FAST_SYNC_CELL:bit_3_FAST_SYNC_CELL , FAST_SYNC_CELL:bit_4_FAST_SYNC_CELL 
 SYNC_PLS
File:lib.v
Instantiates:SR_FF:SR_FF_u1 , SYNC_CELL:go_to_des_SYNC_CELL , SYNC_CELL:back_to_src_SYNC_CELL , pls_gen:pls_gen_u6 
Instantiated by:xmac_sync:rx_good_pkt_sync_SYNC_PLS , xmac_sync:rx_fc_pkt_ok_clk_SYNC_PLS , xmac_sync:inc_max_pkt_err_count_sync_SYNC_PLS , xmac_sync:inc_min_pkt_err_count_sync_SYNC_PLS , xmac_sync:inc_code_viol_count_sync_SYNC_PLS , xmac_sync:inc_align_err_count_sync_SYNC_PLS , xmac_sync:rxfifo_overrun_sync_SYNC_PLS , xmac_sync:inc_crc_err_count_SYNC_PLS , xmac_sync:inc_bcast_count_sync_SYNC_PLS , xmac_sync:inc_mcast_count_sync_SYNC_PLS , xmac_sync:inc_link_fault_count_sync_SYNC_PLS , xmac_sync:rx_fc_pkt_ok_txclk_SYNC_PLS , xmac_sync:TX_PKT_OK_SYNC_PLS , xmac_sync:txfifo_underrun_sync_SYNC_PLS , xmac_sync:txfifo_xfr_err_syn_SYNC_PLS , xmac_sync:tx_max_pkt_size_err_syn_SYNC_PLS 
 sync_r2w
File:sync_r2w.v
 sync_w2r
File:sync_w2r.v
 system_reset
File:system_reset.v
Instantiated by:tb_top:system_reset 
ABCDEFGHILMNOPRSTUVWXZ
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