UltraSPARC T2: A Highly-Threaded, Power-Efficient, SPARC SOC

Conference: This paper was presentated at A-SSCC 2007 (Asian Solid-State Circuirts Conference),  November 12-14, 2007 at Jeju Korea.

Abstract: UltraSPARC T2 is Sun Microsystems’ second generation UltraSPARC T1 processor in essentially the same power envelope. UltraSPARC T2 supports concurrent execution of 64 threads by utilizing eight SPARC cores, each with eight hardware threads. The cores communicate via a high bandwidth crossbar and share a 4MB, eight bank, L2 cache. Each SPARC core includes two integer execution units and a dedicated floating point and graphics unit, which delivers a peak floating point throughput of 11.2 GFLOPS/sec at 1.4 GHz. Each core also has a cryptographic unit. For I/O, UltraSPARC T2 has an integrated x8 PCI-Express channel and two 10G Ethernet ports with XAUI interfaces. Memory is accessed via four on-chip controllers each controlling 2 FBDIMM channels< for a peak memory bandwidth in excess of 60 GB/sec. UltraSPARC T2 is fabricated in an 11 metal, 1.1V, triple-Vt CMOS process. The chip has ~500M transistors on a 342 mm2 die with a power consumption of 84 W at 1.4 GHz. The high level of system integration along with high throughput, floating point, and cryptographic performance makes UltraSPARC T2 an ideal choice for a range of applications including webservers, database and applications servers, High Performance Computing, secure networking, campus backbones, and file servers.

Authors: Manish Shah, Jama Barreh, Jeff Brooks, Robert Golla, Gregory Grohoski, Nils Gura, Rick Hetherington, Paul Jordan, Mark Luttrell, Christopher Olson, Bikram Saha, Denis Sheahan, Lawrence Spracklen, Aaron Wynn 

Technical Paper: “UltraSPARC T2: A Highly-Threaded, Power-Efficient, SPARC SOC”

Slides: “UltraSPARC T2: A Highly-Threaded, Power-Efficient, SPARC SOC”

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