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Abstract:
The recent switch to parallel microprocessors is a milestone in the history
of computing. Industry has laid out a roadmap for multicore designs that
preserves the programmingparadigm of the past via binary compatibility and
cache coherence. Conventional wisdom is now to double the number of cores on
a chip with each silicon generation
A multidisciplinary group of Berkeley researchers met nearly two years to
discuss thischange. Our view is that this evolutionary approach to parallel
hardware and software may work from 2 or 8 processor systems, but is likely to
face diminishing returns as 16 and 32 processor systems are realized, just as
returns fell with greater instruction-level parallelism.
We believe that much can be learned by examining the success of parallelism
at the extremes of the computing spectrum, namely embedded computing and high
performance computing. This led us to frame the parallel landscape with seven
questions, and to recommend the following:
- The overarching goal should be to make it easy to write programs that
execute efficiently on highly parallel computing systems
- The target should be 1000s of cores per chip, as these chips are built
from processing elements that are the most efficient in MIPS (Million
Instructions pe Second) per watt, MIPS per area of silicon, and MIPS per
development dollar.• Instead of traditional benchmarks, use 13 “Dwarfs” to
design and evaluate parallel programming models and architectures. (A dwarf
is an algorithmic method that captures a pattern of computation and
communication.)
- “Autotuners” should play a larger role than conventional compilers in
translation parallel programs.
- To maximize programmer productivity, future programming models must
be more human-centric than the conventional focus on hardware or applications.
- To be successful, programming models should be independent of the number
of processors.
- To maximize application efficiency, programming models should support a
wide range of data types and successful models of parallelism: task-level
parallelism, word-level parallelism, and bit-level parallelism.
Written by:
Krste Asanovíc, Rastislav Bodik, Bryan Catanzaro, Joseph Gebis,
Parry Husbands, Kurt Keutzer, David Patterson,
William Plishker, John Shalf, Samuel Williams, and Katherine Yelick
Presentation: “The Landscape of Parallel Computing Research: A View from Berkeley”
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