Store Memory-Level Parallelism Optimizations for Commercial Applications

IEEE/ACM Int. Symp. Microarchitecture (MICRO), 2005.
With today's database workloads spending almost two-thirds of execution time stalled waiting for DRAM main memory, increasing MLP (memory-level parallelism or the average number of parallel off-chip misses generated by the processor chip) is an important objective in the design of server processor chips. This work demonstrates that even aggressive area- and power-hungry microarchitecture techniques can barely double the MLP of a core for server applications. We came to the realization that for many server workloads, a more effective way is to increase the number of cores and threads supported by the chip, improving the processor chip's MLP by a multiplicative factor. For instance, a server chip with two out-of-order cores may have an MLP of 3 (2X1.5) but a Niagara chip with 32 strands sustains an MLP exceeding 32.

“Store Memory-Level Parallelism Optimizations for Commercial Applications”

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