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Paper presented at the High Level Design Validation and Test Workshop 2007, on November 7-8, 2007 at Irvine, CA.
Abstract: Generating tests to achieve high coverage in simulation based functional verification can be very challenging. Constrained random and coverage-directed test generation methods have been proposed and shown with various degrees of success. In this paper, we propose a new tool built on top of an existing constrained random test generation framework. The goal of this tool is to extract constraints from simulation data for improving controllability of internal signals. We present two automatic constraint extraction algorithms. Extracted constraints can be put back into constrained test-bench to generate tests for simultaneously controlling multiple signals. We demonstrate the effectiveness and scalability of the constraint extraction tool based on experiments on OpenSparc T1 microprocessor.
Bios: Onur Guzey is a Ph.D. candidate in Computer Engineering
at University of California Santa Barbara where he is a Graduate Student
Researcher in Microprocessor Test and Validation Lab. He received
his M.S. degree in Computer Engineering (2006) from UCSB and bachelor degrees
in both Computer Engineering and Electronics and Communication Engineering
(2004) from Istanbul Technical University. He spent the summer of 2007
at Mentor Graphics working in 0-In formal verification group. His current
research interests lie in constrained-random verification, simulation data mining
and statistical learning theory.
Li-C. Wang received M.S. degree in computer science and Ph.D. in electrical and computer engineering from University of Texas at Austin, Texas, USA, in 1991 and 1996 respectively. From 1996 to 2000, he was a Senior Software Engineer at IBM/Motorola Somerset PowerPC Design Center. Since 2001, he has been a faculty member at Electrical and Computer Engineering department, University of California, Santa Barbara, CA. Dr. Wang received best paper awards from Design, Automation and Test in Europe conference in 1998 and 2003, and from IEEE VLSI Test Symposium (VTS) in 1999. He co-founded the IEEE Microprocessor Test and Verification (MTV) Workshop and currently serves as a program committee member for International Symposium on Quality of Electronic Design, Design, Automation and Test in Europe Conference , International Test Conference, International Workshop on High-Level Design Validation and Test, and International Test Synthesis workshop. His current research interests include microprocessor test and verification, performance validation, and applications of data learning in design and test, and he has published more than 90 papers in those areas.
Presentation: Coverage-directed test generation through automatic constraint extraction
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