ACM Int. Conf. Supercomputing (ICS'04), 2004.
These two hardware-prefetching papers illustrate the effectiveness of our simulation infrastructure in evaluating CMT systems as well as techniques directed at HPC workloads. The instruction prefetching strategy must be tailored to the CMT design point. A synthesis of low-cost next-line prefetching together with a discontinuity prefetcher reduces the overall hardware cost while maintaining its effectiveness. Sophisticated mechanisms to control instruction prefetching are needed in CMT systems to ensure that one core's speculative prefetching does not negatively impact other cores' demand misses. Hardware data-prefetching is effective for high-performance computing (HPC) workloads that generally have streaming behavior. The second paper describes a novel stream-prefetcher and shows it to be usually synergistic with other prefetching techniques such as scouting or run-ahead execution.

"Effective Stream-based and Execution-based Data Prefetching"

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