Ana Sonia Leon, Jinuk Luke Shin, Kenway W. Tam, William Bryg, Francis Schumacher, Poonacha Kongetira, David Weisner, Allan Strong IEEE International Solid State Circuit Conference(ISSCC '06), 2006. [Slides]
The 64bit Niagara SPARC processor is designed for power-efficient high-throughput commercial server applications where power, cooling, and space are major concerns. The chip-multithreaded (CMT) architecture achieves high throughput while optimizing performance/watt. Concurrent execution of 32 threads is implemented through 8 symmetrical 4-way multithreaded cores, supported by a high-bandwidth low-latency cache/memory system.

“A Power-Efficient High-Throughput 32-Thread SPARC Processor”

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