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CMT Whitepaper

White Paper: Multithreaded Application Acceleration with Chip Multithreading (CMT)

This white paper highlights the technical benefits Sun's chip multithreading (CMT) UltraSPARC T2 processor delivers to multithreaded applications, and provides detailed examples of significant performance gains in three application workloads: telco, cryptography, and string searching.

White Paper: Multithreaded Application Acceleration with Chip Multithreading (CMT)

 

Technical Papers

The following links are to selected papers Sun has published in some of the top computer architecture conferences. These papers introduce the design challenges motivating chip-multithreading (CMT) processors as well as some of the innovative approaches we have developed. In addition, these research papers indicate how the infrastructure of SPARC systems, tools and traces enables exciting and relevant research in server design. Our plans are to open up a substantial part of this infrastructure to support a vibrant community of researchers on SPARC systems.
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# Article Title Author Hits
1 IWMSE09: Transparent Multi-core Cryptographic Support on Niagara CMT Processors" Hughes, Morton, Pechanec, Scuba, Spracklen and Yenduri 731
2 UltraSPARC T2: A Highly-Threaded, Power-Efficient, SPARC SOC Many Authors 2923
3 HLDVT 07: Coverage-directed test generation through automatic constraint extraction Onur Guzey, Li-C. Wang 1636
4 The Landscape of Parallel Computing Research: A View from Berkeley University of Berkeley 2851
5 MPR: Niagara2 Opens the Floodgates Harlan McGhan (Microprocessor Report) 2932
6 A Power-Efficient High-Throughput 32-Thread SPARC Processor A. Leon, J. Shin, K. Tam, W. Bryg, F. Schumacher, P. Kongetira, D. Weisner, A. Strong 4325
7 Assessment of the Effect of Memory Page Retirement on System RAS Against Hardware Faults Dong Tang, Peter Carruthers, Zuheir Totari, Michael Shapiro 1964
8 Niagara: A 32-Way Multithreaded SPARC Processor Poonacha Kongetira, Kathirgamar Aingaran, Kunle Olukotun 2850
9 Chip Multithreading: Opportunities and Challenges Lawrence Spracklen and Santosh G. Abraham 2113
10 Store Memory-Level Parallelism Optimizations for Commercial Applications Yuan Chou, Lawrence Spracklen, Santosh G. Abraham 1992
11 Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications Lawrence Spracklen, Yuan Chou and Santosh G. Abraham 1908
12 Accurate Modeling of Aggressive Speculation in Modern Microprocessor Architectures Harit Modi, Lawrence Spracklen, Yuan Chou and Santosh G. Abraham 1899
13 Microarchitecture Optimizations for Exploiting Memory-Level Parallelism Yuan Chou, Brian Fahs and Santosh Abraham 2221
14 Effective Stream-based and Execution-based Data Prefetching Sorin Iacobovici, Lawrence Spracklen, Sudarshan Kadambi, Yuan Chou and Santosh G. Abraham 1988
15 TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model Sudheendra Hangal, Durgam Vahia, Chaiyasit Manovit, Juin-Yeu Joseph Lu and Sridhar Narayanan 2022
 
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