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White Paper: Multithreaded Application Acceleration with Chip Multithreading (CMT)

This white paper highlights the technical benefits Sun's chip multithreading (CMT) UltraSPARC T2 processor delivers to multithreaded applications, and provides detailed examples of significant performance gains in three application workloads: telco, cryptography, and string searching.

White Paper: Multithreaded Application Acceleration with Chip Multithreading (CMT)

 

UltraSPARC Architecture 2007 Specification

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Written by Sun Microsystems   
Tuesday, 01 July 2008 03:00
(a.k.a. UA 2007 Family Programmer's Reference Manual)
The UltraSPARC Architecture 2007 is a complete specification of the instruction set architecture (ISA) common to Sun Microsystem's 64-bit SPARC implementations (beginning with UltraSPARC T1 in 2005). UltraSPARC Architecture 2007 complies with SPARC V9 Level 1, with many more details, plus includes numerous Sun extensions common to all UltraSPARC processors. Information in this (and the following) documents can help with Operating Systems ports (including Linux).

The Privileged edition of this document describes the full Nonprivileged (application software) and Privileged (operating system software) levels of the architecture. Download it if you are writing application software, writing a code generator, or writing/porting operating system software to run on top of existing Hypervisor firmware.

The Hyperprivileged edition of this document describes the Nonprivileged, Privileged, and Hyperprivileged (hypervisor/virtual machine firmware) levels of the architecture. Download it if you are writing hyperprivileged firmware ("Hypervisor" code) or designing your own processor based on OpenSPARC.
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