Presented at: Synopsys Users Group (SNUG) 2008, on March 31-April 2, 2008 at Santa Clara, CA.

Abstract: The foundation of RVM is based on the "GoF Design Patterns", for example generators are based on the "abstract factory" pattern and callbacks utilize the "facade and observer patterns". These base level components facilitate re-usability with powerful communication schemes. However the RVM manual is lacking details on the architecture of the next abstract layer of verification components such as checkers, error injectors, configurators and parameter management. This paper will explore verification architecture patterns that address these higher level abstract layers with particular focus on reuse and the "open closed principle". 

Bios: Carl Cavanagh - Carl graduated with a Masters of Engineering degree in Computer Systems Engineering from the University of Bristol in England. He worked for Ensigma Ltd as a research and design engineer for 2 years in Chepstow Wales, where he was the principle verification engineer for a digital radio receiver device. He subsequently moved to California and has spent the last 8 years working for Sun Microsystems. He spent his first 4 years at Sun developing a distributed simulation environment which was applied to server system verification and was awarded 2 US patents. For the past three years Carl was the principle full chip verification engineer for the memory controller in Sun's next generation of high end CMT servers. Currently he is involved in the block level verification of an I/O device.

Chris Sine

Lee Warner

Presentation: “Verification Patterns in Addition to RVM“

Paper: “Verification Patterns in Addition to RVM“