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RAMP Retreat January 2008 Update |
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Written by Sun Microsytems
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Wednesday, 16 January 2008 03:00 |
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Presented at: Sun OpenSPARC team, together with Xilinx, presented the current status
of the port OpenSPARC T1 core on Xilinx FPGAs at RAMP Retreat (http://ramp.eecs.berkeley.edu) on January 16-17, 2008.
Research Accelerator for Multiple Processors (RAMP) is a joint effort
among six Universities (Berkeley, MIT, Stanford, CMU, Austin and UWash)
led by Professor David Patterson to build an emulation infrastructure
for future research in parallel Architecture and Programming.
This presentation show how OpenSPARC is a complete microprocessor solution
- Complete simulation environment with regression suites
- Critical for verifying any changes made to the design
- EDK environment demonstrated on Virtex4 and Virtex5 FPGAs
- Choice of 1-thread or 4-thread cores
- Architectural and simulation models
- Hypervisor API
- OpenSPARC T1 Release 1.6 planned for 1Q2008
- EDK project updates
- MicroBlaze firmware updates for functionality and performance
- ML505-5VLX110T support
- Instructions to boot OpenSolaris
- Complete reference design for 1-thread and 4-thread cores
Presentation: OpenSPARC T1 on Xilinx FPGAs - Update
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