RAMP Retreat August, 2008 Update

Presented at: Sun OpenSPARC team, together with Xilinx, presented the current status of the port OpenSPARC T1 core on Xilinx FPGAs at RAMP Retreat (http://ramp.eecs.berkeley.edu) on August 19-20, 2008.

Research Accelerator for Multiple Processors (RAMP) is a joint effort among six Universities (Berkeley, MIT, Stanford, CMU, Austin and UWash) led by Professor David Patterson to build an emulation infrastructure for future research in parallel Architecture and Programming.

This presentation provides an update on:

1. Availability of the OpenSPARC FPGA Evaluation kit
2. Dual board reference design implementing dual-core T1 on FPGAs
3. Support for Bee3 board by BeeCube - a spin-off from UC Berkeley

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