Abstract: Presentation on Niagara 2 made at the Hot Chips 18 Conference on August 20 thru 22, 2006 at the Memorial Auditorium, Stanford University, Palo Alto, CA

• Niagara-2 combines all major server functions on one chip
• >2x throughput and throughput/watt vs. UltraSparc T1
• Greatly improved floating-point performance
• Significantly improved integer performance
• Embedded wire-speed cryptographic acceleration
• Enables new generation of power-efficient, fully-secure datacenters

Presentation: “Niagara-2: A Highly Threaded Server-on-a-Chip”

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