Home arrow Get Informed arrow Publications arrow Presentations arrow MultiCore Expo Japan 2007: Implementing an OpenSPARC T1 system on an FPGA
MultiCore Expo Japan 2007: Implementing an OpenSPARC T1 system on an FPGA PDF Print E-mail
Written by Thomas Thatcher   
Wednesday, 31 October 2007

Abstract: Presentation made at the MultiCore Expo 2007 Japan, on October 31 and November 1, 2007, Tokyo, Japan.

Bio:  Tom Thatcher graduated from Seattle University with a Bachelors Degree in Electrical Engineering. He worked for 2 years for a startup called Seattle Silicon, which made standard cell compilers, and automated place & route tools. He then went back to school, and graduated from the University of Illinois with a Masters Degree. He went to work for Hewlett-Packard in their California Design Center, where he contributed to ASIC designs for HP's very successful laser printers. Following the HP/Agilent split, he transferred to a Networking group in Agilent, where he worked on mixed-signal PHY chips for Ethernet and FibreChannel systems. He joined Sun in September of 2003, where he has been working on formal verification.

 

Presentation:Implementing an OpenSPARC T1 system on an FPGA

 

Comments (0)add comment

Write comment
quote
bold
italicize
underline
strike
url
image
quote
quote
smile
wink
laugh
grin
angry
sad
shocked
cool
tongue
kiss
cry
smaller | bigger

security image
Write the displayed characters


busy
 
< Prev   Next >
impersonal-mites
Powered By Page_Cache by Ircmaxell
Generated in 0.582828044891 Seconds