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Multicore Expo 2009: Maximizing Multicore Memory Bandwidth Using Compression |
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Written by Lawrence Spracklen
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Thursday, 19 March 2009 09:00 |
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Presented at: MultiCore Expo 2009, on March 16-19, 2009 at Santa Clara, CA.
Abstract: With
the rapidly increasing core-count of multicore processors the memory
bandwidth requirements are also rapidly increasing. In contrast, the
maximum number of pins per package is increasing much more gradually.
This observation is beginning to reignite the old debate that off-chip
memory bandwidth will become a serious bottleneck for multicore
architectures, especially for data-intensive workloads. This
presentation discusses a variety of low-cost compression link
techniques and illustrates their effectiveness at delivering
significant reductions (over 2X) in off-chip memory bandwidth
consumption across a diverse set of workloads, ranging from media
workloads to OLTP (online transaction processing) workloads. Further,
it is illustrated that these improvements can be achieved without
significantly impacting memory latency.
Bio: Dr Lawrence Spracklen
is a senior processor architect at Sun
Microsystems, where he
is focussed on the design & development of
next-generation
multicore processors. Lawrence received a PhD in
Electrical
Engineering from the University of Aberdeen and a BSc in
Computational Physics from the University of York. His research
interests encompass processor architecture, security and
hardware
accelerators.
Dr. Spracklen is the author of a variety of
multicore papers
(including such articles as "The coming wave of
multithreaded
chip multiprocessors" in the International Journal of
Parallel
Programming) and holds 6 US patents. Dr. Spracklen has
presented at IEEE and ACM conferences, acted as session chair
and is a
frequent member of program committees.
Presentation: "Maximizing Multicore Memory Bandwidth Using Compression"
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