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New CMT Whitepaper

White Paper: Multithreaded Application Acceleration with Chip Multithreading (CMT)

This white paper highlights the technical benefits Sun's chip multithreading (CMT) UltraSPARC T2 processor delivers to multithreaded applications, and provides detailed examples of significant performance gains in three application workloads: telco, cryptography, and string searching.

White Paper: Multithreaded Application Acceleration with Chip Multithreading (CMT)

 

Multicore Expo 2007 - Scaling Down from Chip Multicore to Single Core - The OpenSPARC T1 Experience PDF Print E-mail
Written by Durgam Vahia   
Thursday, 29 March 2007

Abstract: Presentation made at the Multicore Expo 2007, on March 27-29, 2007, Santa Clara, CA.

Mapping commercial custom microprocessor like OpenSPARC T1 on FPGAs creates interesting research opportunities in Architectural and Software research. Over the course of last several months, we have been attempting to modify Sun's OpenSPARC T1 design to work with various FPGA vendor tools to create a design point that is an attractive starting point for future research. In this presentation, we will present some of the challenges in mapping full custom design on FPGAs and show a variant of OpenSPARC T1 core that is tailored for a target FPGA device. We will also show how such a platform can be used for creating more interesting hardware prototypes.

 

Bio:  Durgam Vahia is a Staff Engineer at Sun Microsystems and is currently leading OpenSPARC Engineering teams at Sun. In his prior roles, Durgam has led and contributed in various projects in the areas of tools development, logic design and microprocessor verification. Durgam has keen interest in enabling multi-core research in academic institutions by providing out of the box and reconfigurable open-source hardware platform.

Durgam received his MS in Computer Engineering from University of Massachusetts at Amherst.

 

Presentation:Scaling Down from Chip Multicore to Single Core - The OpenSPARC T1 Experience

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