Abstract: Microprocessor architectures have seen the advent of pipelining, branch prediction, superscalar execution, out of order execution and multilevel caching in an effort to improve single threaded performance by exploiting instructional level parallelism. In addition, the trend to higher frequencies has reached the point of diminishing returns as the increasing power and complexity is not matched by corresponding increase in performance.
The large degree of thread level parallelism, low instruction level parallelism and high cache miss rates inherent to commercial server workloads, enables the development of multithreaded processors that are optimised for very high throughput. The UltraSparc T1 processor developed at Sun Microsystems consists of 8 processor cores, each of which is 4 way multithreaded. A simple six stage pipeline implementing 1.2Ghz provides area and power efficiencies while allowing for high throughput. A high bandwidth memory subsystem with banked L2 cache, crossbar interconnect and 4 DDR2 channels provides sufficient memory bandwidth for 32 threads. Microarchitectural details of the various pipestages and clusters are provided.
Bio: Poonacha Kongetira is a Director of Hardware Engineering at Sun Microsystems, and was part of the development team for the UltraSparc T1 both at Sun and Afara Websystems. He has previously worked on a number of Sparc processors. His research interests include computer architecture and methodologies for SOC design. Kongetira has an MS from Purdue University and a BE(Hons) from Birla Institute of Technology and Science(Pilani), both in Electrical Engineering. He is a member of IEEE.

“Microarchitecture of the UltraSPARC-T1 CPU”