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ISSCC 2008: Implementation of a Third-Generation 16-Core 32-Thread CMT SPARC Processor |
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Written by G. Konstadinidis and others
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Monday, 04 February 2008 03:00 |
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Presented at: IEEE International Solid-State Circuits Conference (ISSCC 2008), on Febuary 3-7, 2008 at San Francisco, CA.
Abstract: A 65nm third-generation chip-multithreading SPARC® processor operates at 2.3GHz and is targeted for high-performance servers. It is optimized for both single- and multithreaded applications. Circuit innovations in memory arrays, register files, and floating point hardware boost performance and circuit robustness with minimum area overhead.
Authors: G. Konstadinidis, M. Rashid, P. Lai, Y. Otaguro, Y. Orginos, S. Parampalli, M. Steigerwald, S. Gundala, R. Paypali, L. Rarick, I. Elkin, Y. Ge, I. Parulkar
Presentation: Implementation of a Third-Generation 16-Core 32-Thread CMT SPARC® Processor
Paper: Implementation of a Third-Generation 16-Core 32-Thread CMT SPARC® Processor
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Last Updated on Tuesday, 08 July 2008 05:26 |
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