ISSCC 2008: A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT

Written by M. Tremblay, S. Chaudhry

Monday, 04 February 2008

Presented at: IEEE International Solid-State Circuits Conference (ISSCC 2008), on Febuary 3-7, 2008 at San Francisco, CA.

Abstract: A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC Processor. A 2.3GHz 396mm2 16-core 32-thread processor with deep out-of-order retirement and transactional memory is fabricated in 65nm CMOS. The logical and physical design of this high-end microprocessor enable high throughput, high single-thread performance, mainframe-class reliability, availability and serviceability (RAS), hardware transactional memory, and linear scalability.

Authors: M. Tremblay, S. Chaudhry

Presentation: “A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC Processor“

Paper: “A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC Processor“

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Matt Horsnell: Associated Paper http://www.cs.man.ac.uk/~horsnelm

Hi, Is the first paper referenced available somewhere?

G. Konstadinidis, M. Rashid, P. Lai et al., “Third-Generation 16-core 32-
Thread CMT SPARC® Processor”, ISSCC Dig. Tech. Papers, pp. AA-BB ,
Feb. 2008.

The ISSCC proceedings are not yet available online, and I'd really like to read this in combination with the paper attached above.

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