CMT Whitepaper

This white paper highlights the technical benefits Sun's chip multithreading (CMT) UltraSPARC T2 processor delivers to multithreaded applications, and provides detailed examples of significant performance gains in three application workloads: telco, cryptography, and string searching.

White Paper: Multithreaded Application Acceleration with Chip Multithreading (CMT)

ISSCC 2007: An 8-core, 64-thread, 64-bit, power efficient SPARC SoC (Niagara2)

Written by U. Nawathe, M.Hassan, L. Warriner, K. Yen, B. Upputuri, D.Greenhill, A.Kumar, H. Park

Sunday, 11 February 2007 03:00

Presentation on Niagara 2 made at the ISSCC - International Solid State Circuits Conference 2007 on February 11-15, 2007 at San Francisco Marriott Hotel, San Francisco, CA.

Abstract: Niagara2 is the 1st 64-bit 64-thread SPARC 'System on a chip' from SUN based on the power-efficient CMT architecture optimized for Space, Power and Performance (SWaP). It is the successor to Niagara 1, which is known in the market as UltraSparcT1. It doubles Niagara1's throughput performance, significantly improves Floating point throughput performance, has advanced cryptography support and two 10G ethernet ports on chip.

Bio: Umesh Nawathe is currently a Senior Manager on the Niagara2 project responsible for global/analog circuits and technology. Umesh has an MS(EE) from University of Michigan, Ann Arbor. He joined SUN ~3 years back. Prior to that, Umesh held senior technical and management positions working for MIPS/Silicon Graphics designing MIPS processors and Intel before that.

Presentation: An 8-core, 64-thread, 64-bit, power efficient SPARC SoC (Niagara2)

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