Abstract: Presentation made at the HOT CHIPS 19, on August 20-21, 2007, Stanford, CA.

VictoriaFalls Chip Multiprocessor:

• 8 Core CMP with 8 Strands per Core @ 1.4Ghz
• Niagara2 SPARCv9 Core
• 2 x 8-stage Integer Units (4 Threads per Pipe) – Single Issue per Pipe
• 12-stage Pipelined FGU (except divide/sqrt)
• Integrated Crypto Accelerator
• 16KB 8-way SA L1-I$, 32B Lines, Write-through
• 8KB 4-way SA L1-D$, 16B Lines, Write-through
• 64 Entry Fully Associative I-TLB
• 128 Entry Fully Associative D-TLB
• 4 MB Shared L2$
• 2 Dual-Channel FBDIMM Memory Controllers
• Integrated PCI Express I/O Bridge
• Multi-chip Coherence Links  

Bio:  Stephan Phillips is a Distinguished Engineer with Sun Microystems. He is one of the Architects working on the Victoria Falls processor.

Presentation: “ VictoriaFalls: Scaling Highly-Threaded Processor Cores“