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HLDVT 07: Post-Silicon Verification Methodology on Sun's UltraSPARC T2 Processor PDF Print E-mail
Written by Jai Kumar, Catherine Ahlschlager and Peter Isberg   
Wednesday, 07 November 2007

Presentation made at the High Level Design Validation and Test Workshop 2007, on November 7-8, 2007 at Irvine, CA.

Abstract:

  • Due diligence in pre-si verification to minimize post-si issues
  • Rapid prototyping using HW Emulation is key to enabling virtual silicon bring up before design tape out
  • Debugging in post-si is neither easy nor quick
    • Spend time leveraging, developing & testing tools before you need them: LA, Debug Ports, emulation, formal, debug
    • Build for repeatability in Silicon & Test Generators
    • System debug expertise

Bio: Jai Kumar, Verification Technologist
Catherine Ahlschlager, Manager, Formal Verification
Peter Isberg, Manager, TestGeneration Technologies

Presentation: Post-Silicon Verification Methodology on Sun's UltraSPARC T2 Processor

 

 

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