CMT Whitepaper

This white paper highlights the technical benefits Sun's chip multithreading (CMT) UltraSPARC T2 processor delivers to multithreaded applications, and provides detailed examples of significant performance gains in three application workloads: telco, cryptography, and string searching.

White Paper: Multithreaded Application Acceleration with Chip Multithreading (CMT)

FallMPF '06: Niagara2: A Highly Threaded Server-on-a-Chip

Written by Robert Golla

Tuesday, 10 October 2006 03:20

Abstract: Presentation on Niagara 2 made at the Fall Microprocessor Forum 2006 on October 9 thru 11, 2006 at the Doubletree Hotel, San Jose, CA.

Niagara2 combines all major server functions on on chip

Integrated networking
Integrated PCI-Express
Embedded wire-speed

Niagara2 has improved performance vs. UltraSparc T1

Better integer throughput and throughput/watt (>2x)
Improved integer single-thread performance (>1.4x)
Better floating-point throughput (>10x)
Better floating-point single-thread performance (>5x)

Enables new generation of power-efficient, fully secure datacenters

Bio: Robert Golla has 19 years of microprocessor research and design experience. In his current role as a Senior Designer with Sun Microsystems, he developed the initial microarchitecture for the highly threaded, low power Niagara2 microprocessor and played a key role in its development. Prior to Sun, he architected and developed the embedded e500 microprocessor at Motorola. As part of the IBM, Motorola and Apple Somerset alliance, he played a key role in the design and development of the low power 603 and 603e microprocessors. Prior to Somerset, Robert contributed to the design and implementation of the IBM POWER1 and POWER2 microprocessors.

Robert Golla received his BSEE degree from the University of Houston in 1986 and his MSEE degree from the University of Texas in 1990.

Presentation: Niagara2: A Highly Threaded Server-on-a-Chip

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