Abstract: Designing multi-core multi-threaded processors creates new challanges for EDA tools and IP used in the CMT designs. Some of the problems are similar to problems faced with SOC (System-On-Chip) designs where a high level of integration is required. The presentation includes overview of EDA resources used for UltraSPARC T1 processor design. Using multi-threaded EDA tools running on CMT based servers can benefit significantly to future CMT and SOC designs.
Bio: Raju Joshi, Director of Hardware Engineering, is currently responsible for OpenSPARC engineering. He joined Sun Microsystems in 1988 and managed many Sun hardware design projects including ASICs, board designs which were part of many Sun desktop workstation systems, Multi-processor servers, graphics and Networking cards. Before joining Sun, Raju worked at Valid Logic Systems where he led the Logic Simulator development team. He has BS degree in Electrical Engineering and MS degree in Computer Science.

“EDA/IP Resources for MultiCore Chip Designs”