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DVCon 2007: Issues & Techniques for Dealing with Coverage at Sun |
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Written by Mercedes Tan
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Wednesday, 21 February 2007 |
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Abstract: Presentation made at the DVcon - Design and Verification Conference 2007, on February 21-23, 2007 at the Doubletree Hotel, San Jose, CA.
This presentation focuses on using coverage to track progress and to measure completeness against the verification plan. It discusses the different types of coverage to collect and the challenges with unifying
them to get a comprehensive coverage measurement. It then focuses on functional coverage and the challenges in aggregating the data points
and the multiple simulation runs. Lastly it also discusses various
methods in analyzing coverage holes.
Bio: Mercedes Tan is a Staff Verification Engineer at Sun Microsystems, where
she has been responsible for doing processor verification since 1996.
Currently, she is working in the global formal verification group where
she
is driving deployment of advanced formal verification tools and methodologies. Prior to that, she verified UltraSparc processors as a fullchip, functional verification engineer. She was a contributing
participant in the founding Steering Committee for the Coverage
Interoperability Forum which has now become the Accellera Unified
Coverage Interoperability Standard (UCIS) group. She has a B.S. in
Computer Engineering from San Jose State University.
Presentation: “Issues & Techniques for Dealing with Coverage at Sun”
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