Abstract: Presentation on UltraSPARC T1 made at the A-SSCC 2006 - Asian Solid-State Circuits Conference on November 13-15, 2006 at the Hyatt Regency Hangzhou, China.

This paper presents the UltraSPARC T1:

• Design Metric: Performance per Watt
• 32 Threads hide Instruction and Memory Latency in a short and simple Pipeline
• Large Bandwidth instead of High Frequency delivers Throughput Performance with low Power
• Cooler and more uniform junction temperatures enhance Performance - Reliability Trade-offs.
• The UltraSPARC T1 addresses Performance, Power, and Cooling challenges in Today’s Data Centers

Bio:  Sonia Leon received the M.S. degree in Electrical Engineering from the University of Southern California in 1988. She joined Sun Microsystems in 1999 where she has led and managed the design of several high-performance SPARC microprocessors. She was the Physical Design Manager for the first generation of CMT processors, Niagara, being responsible for foundry interaction, memory design, circuits, design methodology and chip integration. She currently serves as Director of Technology, leading the research and development of advanced design technologies, circuits, memories and methodology for 45nm and 32nm. Before Sun she was with Motorola (Austin) and Chromatic Research (Sunnyvale). She is a Senior Member of IEEE holding several patents and IEEE papers.

Presentation: “The UltraSPARC T1: A Power-Efficient High-Throughput 32-Thread SPARC Processor”