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1 |
HOTCHIPS21: Sun's Next-Generation Multi-threaded Processor - Rainbow Falls
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Sanjay Patel, Stephen Phillips and Allan Strong |
2000 |
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2 |
HOTCHIPS21: Sun's 3rd generation on-chip UltraSPARC security accelerator
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Lawrence Spracklen |
1490 |
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3 |
Multicore Expo 2009: Maximizing Multicore Memory Bandwidth Using Compression
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Lawrence Spracklen |
996 |
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4 |
Slidecast: All About OpenSPARC
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Sun Microsystems |
4468 |
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5 |
HOTCHIPS20: Rock: A third Generation 65nm, 16-Core, 32 Thread + 32 Scout-Threads CMT SPARC Processor
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Shailender Chaudhr |
1661 |
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6 |
RAMP Retreat August, 2008 Update
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Sun Microsystems |
1928 |
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7 |
OpenSPARC T1 FPGA Tutorial (updated for release 1.6)
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Sun Microsystems |
3382 |
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8 |
CommunityOne 2008: Multicore Processors and Microparallelism
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Lawrence Spracklen |
877 |
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9 |
CommunityOne 2008: Techniques for Utilizing CMT
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Darryl Gove |
892 |
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10 |
CommunityOne 2008: Taking Multicore CMT to the Next Level, the Victoria Falls Processor
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Denis Sheahan |
1117 |
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11 |
ESC 2008: Parallelising serial applications
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Darryl Gove |
1444 |
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12 |
MultiCore Expo 2008: Multicore Processors and Microparallelism
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Lawrence Spracklen |
1707 |
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13 |
MultiCoreExpo 2008:Strategies for improving the performance of single threaded codes on a CMT system
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Darryl Gove |
1462 |
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14 |
MultiCore Expo 2008: Hardware and Software solutions for scaling highly threaded processors
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Denis Sheahan |
1083 |
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15 |
SNUG08: Verification Patterns in Addition to RVM
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Carl Cavanagh, Chris Sine and Lee Warner |
5352 |
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16 |
ISSCC 2008: A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT
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M. Tremblay, S. Chaudhry |
2502 |
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17 |
ISSCC 2008: Implementation of a Third-Generation 16-Core 32-Thread CMT SPARC Processor
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G. Konstadinidis and others |
1526 |
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18 |
RAMP Retreat January 2008 Update
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Sun Microsytems |
937 |
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19 |
MICRO-40: Introduction to OpenSPARC
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David Weaver, Juy-chun Wang and Paul Jordan |
2700 |
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20 |
HLDVT 07: Post-Silicon Verification Methodology on Sun's UltraSPARC T2 Processor
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Jai Kumar, Catherine Ahlschlager and Peter Isberg |
1821 |
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21 |
MultiCore Expo Japan 2007: Implementing an OpenSPARC T1 system on an FPGA
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Thomas Thatcher |
1390 |
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22 |
HOTCHIPS19: VictoriaFalls: Scaling Highly-Threaded Processor Cores
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Stephan Phillips |
2720 |
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23 |
Workshop presentation made at Tunxi/Huangshan, China
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David Weaver, Durgam Vahia, Jing Xiong |
1525 |
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24 |
Ramp Retreat June 2007: OpenSPARC T1 on Xilinx
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Durgam Vahia and Paul Hartke |
1722 |
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25 |
WCAE 2007: Industry Perspective on Chip Multi-Threading: Bridging the Gap with Academia
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Shrenik Mehta and Dwayne Lee |
1970 |
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26 |
Synopsys University Reception: Energy Efficient Design - Innovate with OpenSPARC
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Shrenik Mehta |
1695 |
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27 |
Multicore Expo 2007 - Scaling Down from Chip Multicore to Single Core - The OpenSPARC T1 Experience
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Durgam Vahia |
2514 |
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28 |
Multicore Expo 2007 - Open Source Hardware - Myth Becomes Reality
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Fadi Azhari |
2304 |
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29 |
Multicore Expo 2007 - Multicore 'Explo' is a More Fitting Name
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Rick Hetherington |
3108 |
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30 |
Workshop on Recent Trends in Processor Architecture
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Ramesh Iyer, Shrenik Mehta, David Weaver, Jhy-Chun Wang |
2301 |
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