OpenSPARC Community Projects are online areas within OpenSPARC.net where members
can come together and collaborate to develop ideas, code, or anything else
relating to OpenSPARC technology. We\'re just starting to host projects
on OpenSPARC.net. Look through them. You can passively observe a project,
actively participate, or start your own project.
Participating in OpenSPARC.net Projects
You can participate in projects in many different ways, depending on your level of interest:
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Join a project mailing list. Listen in, and/or interact on project discussions,
CVS activity, issues, announcements.
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Join a project. There are different roles you can assume on a project... from
Observer to Content Developer to Developer to Project Owner. Typically you first join a project as an Observer and your role will change as contributions are made.
Projects on OpenSPARC.net contain many tools to enable and promote collaborative
discussion and development. These include mailing lists, source code version
control with CVS, issue tracking, file sharing, and news announcement postings.
Once you\'ve joined a project, you may want to share files or code with other
Project Members. Check with the Project Owner to make sure you have access
to CVS if you wish to post content or other types of files. You must also
have a CVS client installed on your system in order to upload or download
files using CVS. SSH is supported but not required.
If you select the "Version Control" left navigation bar link in a project, and
then follow, "Browse source code", you will be able to see all
of the files (except those shared through the "Document & Files" area) associated with the project.
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The Cool Tools Project intent is to share and discuss tools and resources related to porting or performance optimization in support of OpenSPARC and to foster and encourage the development of OpenSPARC related tools. There are both Cool Tools for Software Development and Cool Tools for Deployment. With more to come in the future.
Join Cool Tools project.
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Faban is the consolidation of our benchmark development and
management knowledge and experience. It is a facility for developing and
running benchmarks. It has two major components, the Faban harness and
the Faban driver framework.
Join the Faban project.
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The FPGA Project intent is to allow FPGA implementation experts to take what was provided with OpenSPARC T1 version 1.1 and to further develop the FPGA implementation including work to optimize area and timing of this design and contribute their changes back to this project and to shared with the community.
Join the OpenSPARC FPGA project.
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The contrib project
- To provide a place for the community to share their contributions with other members of the community.
- For smaller contributions that may not required the overhead of having their own dedicated project.
The first contribution is:
Professor Jose Renau from University of California at Santa Cruz has
contributed his 65 nm synthesis work to the OpenSPARC community. His
scripts takes the OpenSPARC T1 RTL as input and synthesizes them to gates using
Synopsys Design Compiler.
Join the contrib project.
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OpenSPARC T1 Project is the open source version of the UltraSPARC T1 processor. The UltraSPARC T1 processor with CoolThreads technology is the highest-throughput and most eco-responsible processor ever created. It's a breakthrough discovery for reducing data center energy consumption, while dramatically increasing throughput. Its 32 simultaneous processing threads, drawing about as much power as a light bulb, give you the best performance per watt of any processor available.
Join OpenSPARC-T1 project.
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The s1 project
Sun Microsystems' OpenSPARC T1 microprocessor (codename Niagara),
recently released under the GPL license, features 8 SPARC CPU Cores
and several peripherals; the S1 Core takes only one 64-bit SPARC Core
from that design and adds a Wishbone bridge, a reset controller and a
basic interrupt controller, to make it easy for a system engineer to
integrate the design.
Simply RISC S1 Core (codename Sirocco) shares with
the SPARC v9 Core, from which it is derived, the ability to execute
four concurrent threads at the same time; and Operating Systems that
support Sun's microprocessor, such as OpenSolaris and GNU/Linux
distributions (like Ubuntu and Gentoo), will then detect four different
CPUs even if on the chip the CPU core is only one.
Join s1 project. |
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SESC: cycle accurate architectural simulator |
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SESC is a cycle accurate architectural simulator. It models a very wide set of architectures: single processors, CMPs, PIMs, and thread level speculation. SESC started as the pet project of Jose Renau while doing his PhD at Urbana-Champaign in the IACOMA group. Currently, he is a new faculty at University of California, Santa Cruz. It is used by several research groups at the University of Illinois, University of Rochester, North Carolina State University, Georgia Institute of Technology, and Cornell University.
See how you can help with SESC.
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The Transplant project provides the capability for simulating
portions of real-world, full-system workloads on the OpenSPARC
RTL. The key idea is to "transplant" architectural register and
memory state from full-system functional simulators such as SAM
and Simics to the RTL model. This process allows RTL simulation
for workloads such as operating systems and databases that are
otherwise too slow to simulate or require resources (e.g., I/O)
that are not modeled in RTL.
The transplant code is written by Jared Smolens with help from Eric Chung, both
graduate students from the Computer Architecture Lab at
Carnegie Mellon.
Join the Transplant project.
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Get Involved