Prof. Jose Renau is an assistant professor of computer engineering at at the University of California Santa Cruz. He earned his Ph.D. degree in Computer Science from the University of Illinois at Urbana-Champaign. His research focusses on computer architecture, including design effort and complexity estimators, chip multi-processors, energy/performance trade-offs, thread level speculation, processors-in-memory, and checkpointed architectures. He is a member of the IEEE Computer Society and the ACM.

Some work related to the OpenSPARC project: Prof. Renau's team has enhanced SESC to read SPARC instruction traces in the Sun's open-sourced RST format and has successully simulated a Niagara processor using these traces. Prof. Renau is working on interfacing SESC with other tools released from Sun, including the SAM system simulator. Prof Renau and his students are developing SCOORE, a 4-way superscalar out-of-order SPARC processor that is synthesizable on FPGAS and ASIC, in part by leveraging the tools that we are open-sourcing from Sun.

His website: http://www.soe.ucsc.edu/~renau.