New Features in the Release 1.6 of  OpenSPARC T1

• T1 core supports single- and four-thread options on FPGAs
  
• Reference designs boot OpenSolaris on single- or four-thread mode
  
• Xilinx Virtex-5 technology support
  
• Networking (ftp, telnet) support

These new features are designed to enable a user to build real systems using the OpenSPARC T1 core. For further details on Xilinx, please refer to the Xilinx University program.

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Release Notes for Version 1.6

1. Xilinx FPGA support for Virtex 5 FPGAs
   1. EDK and ISE Version 9.2 support
   2. EDK project for ML505-V5LX110T board (An ML505 board upgraded to an XC5VLX110T)
   3. Pre-synthesized 4-thread core netlist
2. Retained Xilinx Virtex 4 Support
   1. Identical EDK 9.2 project for ML411 board (XC4VFX100)
3. Support for OpenSolaris Operating System boot
   1. Hypervisor support for 1-thread and 4-thread cores
   2. Minimal OpenSolaris RAM disk image.
   3. Sample ACE file provided to allow out-of-the box booting of OpenSolaris
4. Support for networking
   1. Telnet, FTP to and from the board.
5. Improved CCX Firmware code.
   The memory subsystem is emulated using a MicroBlaze core. Here are the improvements that have been made to this code:
   1. Improved performance
   2. Support for networking
6. Miscellaneous Improvements
   1. Several scripts have been re-written to improve the user interface.
   2. Documentation has been updated and improved.

1. Floating-point support in Firmware.
   Currently, the CCX firmware emulates the floating-point processing for the floating-point unit, because that unit is not included in the FPGA project. Approximately 50 diagnostic tests in the core1_full regression which exercise the floating-point unit fail when run on the FPGA project. The cause is probably due to the emulation code not supporting some special cases. These cases have been commented out of the core1_full test list.
2. Full-system simulation needs to run longer.
   The procedure to run a full-system simulation of the FPGA system containing the OpenSPARC T1 core is described in the "OpenSPARC T1 Design and Verification Guide" in Chapter 6. The script $DV_ROOT/design/sys/edk/do_sim_mb.do currently runs for 7ms. However, due to recent code changes which added networking support, the system spends more time initializing the data segment of the CCX firmware code. This means that the simulation must run longer in order to see any meaningful operation of the OpenSPARC core.

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