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OpenSPARC T1 is the open source version of the UltraSPARC T1 processor.
The UltraSPARC T1 processor with CoolThreads technology is the
highest-throughput and most eco-responsible processor ever created.
It's a breakthrough discovery for reducing data center energy
consumption, while dramatically increasing throughput. Its 32
simultaneous processing threads, drawing about as much power
as a light bulb, give you the best performance per watt of any
processor available.
By making the source for this design available
for a larger community to review and learn from, we expect that ideas
around the multi-thread concepts can be explored more freely and
openly, and that truly beneficial innovations can be achieved.
Please join our Mailing List to get up-to-date announcements.
Both downloads are available from the Sun Download Center.
OpenSPARC T1 Download for Chip Design and Verification
OpenSPARC T1 chip source code is for hardware engineering community
with experience in chip design and verification.
OpenSPARC T1 source components are covered
under multiple open source licenses. The majority of OpenSPARC T1 source
code is released under the GNU General Public License.
Source based on existing open source projects will continue to be
available under their current licenses.
Binary programs are released under a binary Software License Agreement.
This download area is for hardware design and verification engineers, it includes
- Verilog RTL for OpenSPARC T1 design
- Verification environment for OpenSPARC T1
- Diagnostics tests for OpenSPARC T1
- Scripts and Sun internal tools needed to simulate the design and to do synthesis of the design
- Open source tools needed to simulate the design
- Scripts and documentation to help with FPGA implementation of parts of OpenSPARC T1 design including SPARC core, Floating point Unit, Cross-bar
System Requirements:
- SPARC CPU based system with Solaris 9 or Solaris 10 Operating System
- x86 CPU based system with Solaris 10/x86 or Red Hat Enterprise Linux 3/x86 Orating System
- C/C++ Compiler, if you don't have it download Sun Studio
12 (it's free too!).
Commercial EDA tools Requirements:
- Verilog Simulator : Synopsys VCS® or Cadence NC-Verilog®
- Synthesis : Synopsys Design Compiler® or Synplicity Synplify Pro®
OpenSPARC T1 Download for Architecture and Performance Modeling Tools
SAM (SPARC Architectural Model) is a full system simulator that is able
to boot Hypervisor, OBP(Open Boot PROM) and Solaris and run applications.
It loads SAS (SPARC Architecture Simulator) as the OpenSPARC T1 simulator. So
any modifications made in SAS get automatically reflected in SAM. SAM
is useful for software bringup work -- for instance to debug
Hypervisor/OBP/Solaris on a modified CPU implementation. SAM is also useful
for performance analysis, both to generate traces and to connect with a
performance model to perform execution driven simulation. SAM loads device
models as dynamically linked libraries, and is useful for device driver
development, and device rtl verification.
Legion is a fast instruction accurate simulator
which provides a rapid means of developing and testing
software functionality in the absence of actual hardware.
Legion provides the fastest simulation environment for developing and
testing SPARC Software. Firmware and Software developers will
be the primary users of Legion simulation
environment for the OpenSPARC T1.
OpenSPARC T1 source components are covered under multiple open source
licenses. The majority of OpenSPARC T1 source code is released under the GNU General Public License.
Source based on existing open source projects will continue to be available
under their
current licenses. Binary programs are released under a binary Software License Agreement.
The Hypervisor and OBP source code is released under BSD license.
This download area is for software engineers and architects, it includes
- SAM - SPARC Architecture Model (including source code)
- Legion - Fast instruction accurate simulator for software developers (including source code)
- SAM/Legion enhancements to copy files to/from simulated disk
- SAS - Instruction accurate SPARC Architecture Simulator (including source code)
- OBP - Open Boot PROM source code
- Hypervisor source code
- Solaris Images for simulation
- RST Trace Tool - RST is a trace format for SPARC instruction-level traces. The RST
Tools package consists of the trace format definition, a trace reader/writer
library, and a trace viewer program. Also included is a sample trace from a
32-strand application.
System Requirements:
- SPARC CPU based system with Solaris 9 or Solaris 10 Operating System
- C/C++ Compiler, if you don't have it download Sun Studio
12 (it's free too!).
Downloads
- Step 1: Download one or both of the following files and then use bunzip2 command to create
OpenSPARCT1.x.x.tar file. e.g. bunzip2 OpenSPARCT1.1.0.tar.bz2
OpenSPARC T1 Chip Design and Verification download
OpenSPARCT1.1.6.tar.bz2 (bzip2 compression, 169,341,013 bytes)
OpenSPARC T1 Architecture and Performance Modeling download
OpenSPARCT1_Arch.1.5.tar.bz2 (bzip2 compression, 198,858,700 bytes) Both downloads are available from the Sun Download Center.
- Step 2:
Use the following command to extract files from tar file : tar xvf OpenSPARCT1.x.x.tar
- Step 3:
For the Chip Design and Verification download, please follow the instructions in the README file in the
download to run simulations or synthesis. Also refer to Design/Verification Users Guide document
included in the download.
For the Architecture and Performance Modeling download, please follow the instructions in
the README file in the download to setup and run SAM.
OpenSolaris Boot
Here is the ACE file required to boot OpenSPARC on the Xilinx FPGA board and a Quick Start guide. These are included in the download but are
listed here so you don't need to download the whole tarball.
Related Tools
Shade - is a fast SPARC instruction set simulator that is used to perform a variety of analysis functions on SPARC executables.
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Get The Source 
