TMWorld.com: Power-aware test hot at ITC, as is analog test

Power-aware test will be the focus of a panel discussion and two technical paper sessions and is a key topic at this year’s International Test Conference, says Nur Touba, Professor, Department of Electrical and Computer Engineering, University of Texas at Austin, and Program Chair of this year’s ITC. The conference and associated Test Week presentations, to be held October 26-31 in Santa Clara, CA, will also focus on other hot topics, Touba says, such as analog test, which will be addressed in an interactive talk with analog legend Bob Pease. Events of note include a new poster session, a panel on university DFT implementations and a new workshop on design for reliability and variability. Touba discussed this year’s ITC in a phone interview.

Power-aware test will be the focus of a panel discussion and two technical paper sessions and is a key topic at this year’s International Test Conference, says Nur Touba, Professor, Department of Electrical and Computer Engineering, University of Texas at Austin, and Program Chair of this year’s ITC. The conference and associated Test Week presentations, to be held October 26-31 in Santa Clara, CA, will also focus on other hot topics, Touba says, such as analog test, which will be addressed in an interactive talk with analog legend Bob Pease. Events of note include a new poster session, a panel on university DFT implementations and a new workshop on design for reliability and variability. Touba discussed this year’s ITC in a phone interview.

The theme of last year’s conference was “facing nanometer test challenges.” What’s this year’s theme?

The steering committee decided not to have a theme this year. The thinking was it really wasn’t driving the program a lot beyond possibly the selection of the keynote speaker.

Who is the keynote speaker this year?

Mike Lydon, VP of test and quality at Cisco, will deliver the keynote address, which is titled “Managing Test in the End-to-End, Mega Supply Chain.” He’s going to talk about managing the supply chain and using test to make real-time end-to-end adjustments over the product’s lifecycle.

Will you have invited addresses?

Yes, we have three invited talks. Just like last year, they will be after lunch each of the three days of the conference.

In the first one, “Computing at the Crossroads (and What Does it Mean to Verification and Test?),” Jan Rabaey of the University of California, Berkeley, will talk about how technology scaling, distributed computation, and physical models of computing will all have a profound effect on how we verify and test designs in the future.

The second talk—“Having FUN with Analog Test—will be given by Bob Pease, staff scientist at National Semiconductor and a legend in the analog community with 48 years of experience. He’s going to be having an interactive conversation—answering questions from the audience—which is something new for an ITC invited address.

Third talk will be given by Jeff Rearick, AMD Fellow, who will talk about how to tell if DFT and test are adding value to your company and how to justify your investment in test.

What are the program highlights this year?

We have added several new features to the program. One is a poster session, which differs from what some conferences do. Some conferences invite regular paper submissions that don’t make the cut to be presented as posters. What we’ve done is have a totally separate submission and review process for the posters. The thinking is, there are some people out there who have some really interesting data, but they don’t have time to write up a 10-page paper about it. The poster submissions require only a one-page summary, so it makes it easy for busy people to come and present their data.

Also, while the regular paper submission deadline was in February, the poster submission deadline was in July, which allows people to submit more late-breaking results. And by presenting a poster, they can get some feedback that helps them write a full paper for the next ITC. In addition, with the poster session we encouraged people to submit on nontraditional topics that wouldn’t necessarily be appropriate as research papers.

When is the poster session?

After the Wednesday afternoon panels last year we held a wine and cheese party. This year on Wednesday we are having an Oktoberfest party, and it’s during that party that the 27 posters will be presented. The presenters will have laptops available to show demos.

What about tutorials?

Another new feature we have this year is embedded tutorials. Of course we will have the 17 tutorials on Sunday and Monday, like we’ve had in the past, but the embedded tutorials will take place on Tuesday morning, during the conference itself. They are included with your registration—you don’t have to pay extra for them. One on mixed-signal production test will be presented by Gordon Roberts of McGill University. In another, Robert Daasch of Portland State University will provide an introduction to statistics and test. He’ll specifically address outlier screening.

Is there a particular hot topic this year?

A topic that is hot this year is power-aware test. We got four panel proposals on that topic. [The selected panel, “Power-aware DFT¯Do We Really Need It?” will run from 5:00 p.m. to 6:30 p.m. Monday.] We also have two full sessions worth of papers on the topic.

We’ve also added another new feature to the conference this year—what we call “hot topic background” sessions. Power-aware test will be the focus of one such session. The background session [scheduled for 8:00 a.m. to 8:30 a.m. Wednesday] will take place in the same room as and right before the two sessions worth of papers on the topic.

What are the other hot topic background sessions?

There’s one more, “Overview of Test Generation and Analysis for Reducing Test Escapes,” on Thursday morning.

You mentioned the panel on power-aware test. What are other panel topics?

We have one very interesting panel, called the University DFT Tool Showdown. [It’s scheduled from 4:15 p.m. to 4:45 p.m. Wednesday.] Sun has made its OpenSPARC T1 and T2 processors available to universities, and during the workshop, four universities are going to demo their tools using these open-source commercially available processors. It will be interesting to see whether the universities can beat the industry in handling these real designs. A lot of university research is tried out on toy benchmark circuits, so there is always some skepticism about whether the results can really scale to industrial-sized circuits. Judges will evaluate these university tools and will give out a $2500 prize to the best one.

What’s the total panel lineup this year?

We have a total of six panels altogether. On Monday evening will be the one on power-aware DFT. Others, scheduled for Wednesday evening, include the university tool showdown as well as panels on analog test, test compression, debug war stories, and yield learning (see related post, "ITC panel to address yield learning: who pays, who gets the data").

There seems to be more emphasis on analog test this year.

Yes, what we found by looking at the attendee feedback was that there is a lot of interest in the mixed-signal and analog sessions, so we have good coverage this year.

What about board and system level test?

We are going to have some regular papers and sessions, and we’ve also got a lecture series on practical issues in board test. [It’s scheduled for 2:00 p.m. to 3:30 p.m. Wednesday.]

And in terms of system test—we are having a joint session with Autotestcon on DFT at the system level. Autotestcon’s attendee base is very different from ITC’s. It’s almost totally nonoverlapping, and we see a lot of benefits in joint sessions. [The Autotestcon joint session is scheduled for 2:00 p.m. to 3:30 p.m. Thursday.]
 
What about workshops after the conference?

We have two workshops continuing from last year: ATE Vision 2020 and a workshop on defect- and data-driven testing. We also have one new workshop this year, which is on design for reliability and variability, which will address design and test innovations that can enabling chips to maintain acceptable reliability levels at reasonable cost.

For more information, visit www.itctestweek.org.

Read the original article: http://www.tmworld.com/article/CA6602403.html?industryid=47185

Comments (0)

Subscribe to this comment's feed

Show/hide comments