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There is still enough competition in the Unix space to
make vendors hate to see each other get the limelight. Which is one of
the reasons why Sun Microsystems
has timed the launch of its "Victoria Falls" Sparc T2+ multicore
processor and the related "Maramba" server line in the same week that IBM is launching big Power6 boxes and Hewlett-Packard is rolling out an update to its HP-UX Unix and a repackaging of the software.
The launch of the Victoria Falls processor and the two Maramba servers are basically what I told you they would be back in March.
The Victoria Falls chips is a variant of the "Niagara-2" Sparc T2
processor that has had two of its memory controllers removed as well as
the integrated "Neptune" 10 Gigabit Ethernet ports and replaced them
with symmetric multiprocessing links that use some of the memory lanes
on the processor to lash the two caches in the chips together into a
two-way processor complex. The Niagara-2 chip runs at 1.2 and 1.4 GHz
and has eight eight-threaded Sparc cores, and with the Victoria Falls
design, Sun is able to put a two-socket Sparc T2+ server into the
field, thereby making the Niagara designs more scalable and therefore
more appropriate to the huge installed base of UltraSparc-II and
UltraSparc-III iron sitting out there in the data centers of the world.
The
talk out there in the blogosphere has made much of the fact that the
Victoria Falls chip only has two memory controllers compared to the
four memory controllers in the Niagara-2 chip, and has been critical of
Sun's decision to remove the Neptune ports from the chip, too. The
memory controller count is not an issue, explains Mat Keep, product
manager for Niagara systems at Sun, and in fact, the Victoria Falls
chip has sufficient memory bandwidth for the jobs it is intended for.
Ditto for the integrated networking, which is not as necessary for the
Maramba servers, which are aimed at database and application serving,
as they were for the Niagara-2 class servers, code-named "Huron" and
aimed at Web infrastructure workloads that were sitting on the edge of
the network and hence where network performance is a competitive
advantage.
As for the
memory controller issue, Keep says that the original Niagara-2 chip
design was going to use DDR2 main memory instead of Fully Buffered DIMM
main memory because FB-DIMM memory was a lot more expensive, and
because of the lower performance of DDR2 memory, Sun therefore planned
to have twice as many memory controllers as you might expect. Then, at
the last minute before Sun taped out the Niagara-2 chips, FB-DIMM
memory prices dropped, and Sun switched to this technology while
keeping the same number of memory controllers. The upshot is that the
Niagara-2 chips delivered just under 60 GB/sec of memory bandwidth for
a single socket machine, which is a lot of bandwidth. The Victoria
Falls design delivers just 38 GB/sec of memory bandwidth per socket, or
76 GB/sec for the whole two-socket system, and that is not a big
improvement. (The Niagara-2 chip had four controllers, but just two
DIMMs per channel, compared to the Victoria Falls chip, which has two
controllers but four DIMMs per channel.) Keep says that the Niagara-2
designs had way more bandwidth than the processors needed because of
the design switch. The reality is, with the Sparc T2+ chip having the
same pinout as the Sparc T2, you have to give up something if you want
to create an SMP chip, and memory controllers and integrated networking
is what Sun decided to give up. The market will decide if Sun did the
right thing or not.
The
market is probably going to be pleased, particularly customers with
Sparc/Solaris applications who want to get off aging iron in the way
that is least disruptive to applications. The jump from the Sparc T1 to
the Sparc T2 chip was a factor of two in performance gain, clock for
clock and core for core, and that was just because the chip went from
32 to 64 threads. (Obviously, that 2X performance is for software that
likes threads; single-threaded jobs might see only a tiny performance
boost, or none at all.) The Sparc T2 added a floating point unit for
each core in the chip, as opposed to a single unit shared by all the
cores, which helped performance on math-sensitive workloads. According
to Keep, customers jumping from the Sparc T2 systems to Sparc T2+
systems will see anywhere from 1.8 times to more than 2 times the
performance, and again, a lot of that is just because the thread count
in the system is jumping from 64 to 128. The clock speeds on the T2+
chip are still at 1.2 GHz or 1.4 GHz, which is a bit disappointing. Sun
should be able to get the clocks up in this chip to 2 GHz or higher,
but is probably keeping speeds low to keep main memory and CPU cycle
times closer together, thereby boosting the overall efficiency of the
system. The other approach would be to use lots of L2 and L3 cache and
crank clocks up to 3 GHz, but that burns more energy to add
performance. (The Victoria Falls T2+ chip has 4 MB of L2 cache on the
die, which is a relatively modest amount.) Energy goes up on a log
scale as performance goes up on a linear--and relatively flat--scale.
The
Maramba servers come in two flavors. The T5140 is a 1U rack-mounted
server that can be equipped with T2+ chips running at 1.2 GHz with
four, six, or eight cores activated per CPU socket. (The more cores
activated, the higher the price.) This box has 16 memory slots, and
supports from 8 GB to 64 GB of main memory using 1 GB, 2 GB, or 4 GB
DIMMs. The system has room for up to four small form factor SAS drives
in 73 GB or 146 GB capacities, and has four Gigabit Ethernet ports and
three PCI-Express x8 peripherals on the board as well (two of them can
be converted to support 10 Gigabit Ethernet XAUI connections). The
entry configuration of this T5140 box comes with two T2+ processors
with four cores activated (64 threads in total) and running at 1.2 GHz,
plus 8 GB of memory and two 146 GB disks for $14,995. A machine with
six active cores per T2+ chip (96 threads) and 16 GB of memory costs
$16,995, and a machine with the full 128 threads turned on in the box
plus 32 GB of memory costs $29,995.
The
Maramba T5240 is a 2U rack-mounted server that has room for up to 16
2.5-inch SAS drives and a DVD player. It sports two T2+ chips linked
together with four, six, or eight cores running at 1.2 GHz or eight
cores running at 1.4 GHz. The machine has 32 memory slots, and main
memory can scale from 8 GB to 128 GB. The machine has the same four
Gigabit Ethernet ports on the board as the T5140 server, but it has
more expansion slots, with four six PCI-Express x8 slots (two again
convertible to 10 Gigabit Ethernet XAUI connections). The base T5240
costs $17,995, and it has two six-core T2+ chips (96 threads) running
at 1.2 GHz, 8 GB of main memory, and two 146 GB disks. Activating all
the cores running at 1.2 GHz and increasing main memory to 32 GB drives
the price up to $31,995 with two disks. Sun did not provide pricing for
a machine with the 1.4 GHz cores on its Web site.
Both
Maramba servers come with Solaris 10 8/07 (Update 4) preinstalled on
the boxes; a whole bunch of Sun middleware and development tools are
also preinstalled. While the initial Niagara-1 machines supported Ubuntu
7.04, this Linux variant is not yet available on the Sparc T2 or T2+
machines. The Linux kernel has had support for the T1 architecture
since April 2006, so it is just a matter of the Linux distros adding
and testing this code for their implementations of Linux. Gentoo (a Debian variant like Ubuntu) and CentOS (a clone of Red Hat
Enterprise Linux) have both just completed work on support for the T1
chips and are moving ahead to the T2 and T2+ chips, according to Keep,
and the OpenBSD Unix project has just finished up its T1 support, too.
Next week, we'll talk about how Victoria Falls is just the beginning of a more scalable Niagara product line.
Read the original article: http://www.itjungle.com/bns/bns040908-story03.html
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