|
Through new research, standards and
tools, the industry is just starting to address what's being called a
software gap between a rising tide of multicore processors and a lack
of parallel programming tools and techniques to make use of them.
The gap came into stark focus in the embedded world at the Multicore Expo
here this week, where chip makers Freescale, Intel and MIPS and a
handful of silicon startups sketched out directions for their multicore
products. Others warned that the industry has its work cut out for it
delivering the software that will harness the next-generation chips.
"There is a major gap between the hardware and
the software," said Eric Heikkila, director of embedded hardware
research at Venture Development Corp. (VDC; Natick, Mass.).
About 55 percent of embedded system developers
surveyed by VDC said they are using or will use multicore processors in
the next 12 months. That fact is fueling the company's projections that
the market for embedded multicore processors will grow from about $372
million in 2007 to $2.47 billion in 2011.
In the PC market, the figures are even more
dramatic. About 40 percent of all processors Intel shipped in 2007 used
multiple cores, but that will rise to 95 percent in 2011, said Doug
Davis, general manager of Intel's embedded group.
But on the software side, vendors reported that
only about 6 percent of their tools were ready for parallel chips in
2007, a figure that will only rise to 40 percent in 2011, VDC said. As
much as 85 percent of all embedded programming is now done in C or C++,
languages that are "difficult to optimize for multicore," said
Heikkila.
"There's a need for a short-term fix to make
C/C++ more expressive, as well as a long-term solution with new
languages and tools," he said.
Changing techniques could be as hard as
developing new tools, according to Alan Gatherer, chief technology
officer of the communications infrastructure group at Texas
Instruments. "We are dealing with legacy methodologies as much as
legacy code," he said.
"If you go to companies such as Ericsson, they
have hundreds of programmers writing code in very disciplined ways. So
a lot of new software ideas are going to have to prove themselves,
because you can't turn an oil tanker on a dime," said Gatherer.
Michael McCool, chief scientist of startup
RapidMind, called for a new programming model to help developers better
understand how to optimize their applications for parallel chips. Such
a model would need to automate as much as possible while giving users
override options and drill-down mechanisms, McCool said.
"Complexity [in multicore programming] explodes beyond a certain point, and that point is fairly low," he said.
The fundamental issues behind creating a
mainstream parallel programming model are just starting to come to
light. "I think we are beginning to see where the heads of the monsters
are," said Wen-mei Hwu, a veteran researcher in parallel programming
and professor of engineering at the University of Illinois at
Urbana-Champaign.
The university recently won a $10 million grant
from Intel and Microsoft to explore new parallel programming
techniques. "There is really only room for one model of parallel
programming. No one can afford to write applications in multiple
models," said Hwu.
As co-chair of the university's new parallel
research center, Hwu said he wants to build programming frameworks to
limit variables such as dependencies in parallel software that create
thorny problems for compilers. "We believe the frameworks should also
serve as a source of information available to the compilers and
underlying hardware," he said.
The university will partner with another center
funded by Microsoft and Intel at the University of California at
Berkeley. "It's not a competitive situation," said Hwu.
Separately, Illinois researchers are seeking
$10 million to create a next-generation parallel processor. Called
Rigel, the chip aims to anticipate future many-core processors by
extrapolating directions in today's general-purpose multicore computer
and graphics chips.
Sanjay Patel, who designed the physics
processor from startup Ageia Technologies (recently acquired by
Nvidia), will lead the chip design. Hwu will lead work on applications
for the chip in areas such as video surveillance. The team has set an
ambitious goal of defining a range of chips from a 1-watt Teraflops
processor to a 100-W 10-Tflops CPU.
Setting standards
In terms of standards, the Multicore
Association announced at the Expo it has completed work on an
applications programming interface for communications between cores,
and is now working to define a standard for embedded virtualization.
Observers praised the efforts and pointed to
related work-in-progress at groups such as the Mobile Industry
Processor Interface, OpenMP, Posix and Power.org.
"Multicore is forcing companies to open up and
drive new business models. There is a requirement for more
standardization than ever before," said Heikkila of VDC.
However, experts are still advising caution in
the area of designing new languages or making major extensions to
existing ones to better serve parallel chips.
"The ultimate goal of every computer scientist
is to create a new language, but my personal view is we should not do
it this time around," said Hwu, referring to a flowering of languages
developed for big parallel computers two decades ago, many of which
never gained traction.
"I believe there will be new language
constructs in C/C++ to support some of the new frameworks people will
develop, but even these constructs, if we are not careful, will not be
widely adopted," Hwu said. "Ultimately, I think we will make a small
amount of extensions to C, but I think it's too early.
"If you really want to have a million people do
something, don't ask them to speak Latin. It is enough to ask them to
just speak English without using cuss words," he quipped, explaining
the need for an evolutionary approach.
Following that route, researchers from IMEC
(Leuven, Belgium) described a handful of new tools based on what it
called CleanC. Diederik Verkest, a group science director for the
research institute, described it as a C variant that follows 28 "common
sense" rules to smooth the path to parallelism.
"Following these practices is a good thing to do if you want to have the best chance of analyzing your code," said Verkest.
One of the new IMEC tools aims to hide the
complexity of new memory hierarchies and interconnect fabrics
increasingly used in multicore chips. Another tool quickly shows
scaling benefits of a program without requiring the program to be
debugged.
"We believe compiler-like tools in the hands of smart programmers is the best way to get to parallel code," said Verkest.
Hardware moves on
On the hardware front, MIPS Technologies came to the Expo with details
of its first multiprocessing-ready core. The 1004K aims to leapfrog
existing products from its archrival ARM Ltd.
For their part, Freescale and Intel sketched out design trends they see on the horizon for their multicore chips.
Freescale is now sampling the first dual-core
versions of its PowerQuicc processors, aimed at telecom OEMs. The chips
are part of a family that will eventually scale to 32-core devices,
said Dan Cronin, vice president of R&D for Freescale's networking
division.
The processors will use a new on-chip
interconnect fabric. They will also embed in hardware a hypervisor, a
kind of low-level scheduling unit, co-developed with IBM according to
specs set in the Power.org group. Freescale will release an open source
reference design for companies that want to build virtualization
software that taps into the hypervisor, Cronin said.
"Several other processor companies are doing
similar things" with embedded hypervisors, raising the issue of
non-standard approaches to virtualization, said Marcus Levy, president
of the Multicore Association and host of the expo.
Intel described several extensions it sees on
the horizon for its multicore chips, including new on-chip fabrics,
scratchpad memories and use of spare cores and schedulers. "Beyond
adding to the sheer number of cores, there are several system-level
challenges that need to be overcome to tap into the true power of
multicore processors," said Pranav Mehta, chief technologist of Intel's
embedded group.
Asked how many engineers Intel has working on
multicore programming issues, Mehta said, "If I had to guess, I would
say it is at least in four digits, but even Intel doesn't think we can
solve all the problems here alone."
A handful of chip startups, including Ambric
and Intellasys, came to the expo touting novel multicore architectures
and proprietary tools to write software for them. One of the newer
companies among them, Plurality Ltd. (Netanya, Israel), said it will
release a 256-core product early next year and simulation models and
tools for using it in the next few months.
Read the original article: http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=207001633
 |
Get Informed 
Subscribe to this comment's feed
Show/Hide comments