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Just after The Linux Beacon went on holiday in December, server and operating system maker Sun Microsystems
not only reminded the IT industry that it still makes its own
microprocessors for servers, but that it is taking the open sourcing of
its technologies deadly seriously. Having taken the design of the
"Niagara" Sparc T1 processor open source through the OpenSparc
project only three months after the Niagara chips appeared in products,
Sun has done it again with the "Niagara-2" Sparc T2 kickers.
Just after The Linux Beacon went on holiday in December, server and operating system maker Sun Microsystems
not only reminded the IT industry that it still makes its own
microprocessors for servers, but that it is taking the open sourcing of
its technologies deadly seriously. Having taken the design of the
"Niagara" Sparc T1 processor open source through the OpenSparc
project only three months after the Niagara chips appeared in products,
Sun has done it again with the "Niagara-2" Sparc T2 kickers.
This
time, the gap between a production chip and the open sourcing of its
design is even smaller--just two months. The Sparc T2 chips went into
production Enterprise T5120 and T5220 servers in October, and the
specifications for the chip as well as the Register Transfer Level
(RTL) designs for it are available as of the middle of December through the OpenSparc site.
Sun taped out the Sparc T2 design in April 2006, and launched the T2
chip as it broke chip development from servers in a reorganization in
March 2007. That reorganization saw Sun merge its server and storage
units and spin out chips again, as they had been in days gone by.
As previously reported,
the Sparc T2 chip has eight processor cores, each with eight threads
and each with a floating point unit. (Clock for clock, this design
provides about twice the oomph of a Sparc T1 chip on integer workloads,
since the T1 has only four threads per core; the T1 chip has only a
single floating point unit shared by all eight cores, so the T1 can
actually do math calculations without taking its shoes off.) The T2
chip has 4 MB of L2 cache, one x8 PCI-Express slot, two 10 Gigabit
Ethernet ports (which are a variant of the "Project Neptune" 10 GE chip
that Sun has designed), and an on-chip memory controller that can drive
eight FB-DIMM memory slots. The T2 chip has 500 million transistors and
a 342 square millimeter die size; it is implemented in an 11-layer, 65
nanometer process from Texas Instruments.
The Sparc T1 chip had 1,111 pins and its socket was considerably larger
than the T2 chip, which has only 720 pins. Of those 720 pins on the T2
chip, 200 are used for testing the chip, so you can see that Sun's new
serial I/O design with the T2 chip is a lot more streamlined than the
hybrid serial and parallel links used in the T1 chip. This gives the T2
chip higher bandwidth between components, and it also lays the
groundwork for the multi-socket "Victoria Falls" Sparc T3 kickers--if
they are going to be called that, Sun hasn't said--which are due in
systems from Sun and Fujitsu-Siemens
sometime in the first half of 2008. The Sparc T2 can only be used in
single-socket servers, just like the Sparc T1 chip, but with the
Victoria Falls chips, Sun could gang up two or four of these into a
single system image and build a very powerful midrange box. And it
almost certainly will.
The
question, of course, is will anyone else build server-class chips based
on the T1, T2, and T3 chips, should the latter be open sourced as well?
It is hard to say if Sun really wants that to happen. But the
company is clearly pleased that since March 2006, when the RTL files
and the T1 specification first went up on the OpenSparc site, more than
6,500 copies of these files have been downloaded by competitors,
partners, software developers, and other interested parties, such as
universities. When the T2 design went into beta in August, people were
lining up to get an early peek at it, too, says Shrenik Mehta, senior
director of front-end technologies and OpenSparc at Sun. (OK, it was
150 people, but that is a lot for a chip design--a lot more than many
might have expected.)
"People
definitely want to learn about the Niagara chips, and colleges and
universities are beginning to put the chips into the computer science
courses," says Mehta. Two major compsci text books now have chapters on
the Niagara chips and their multithreading and efficient computing
designs. In many cases, compsci courses are using a single-core Niagara
design with one or four cores implemented as a field programmable gate
array (FPGA), which can be designed and tweaked using Xilinx tools, as a basic computing building block for students to learn from.
Of course, Simply RISC,
the Anglo-Italian chip startup, has implemented three different
variants of the T1 chip, which it nicknamed the "Sirocco" S1 chip. The
S1 chip was created by taking a single T1 core and implementing it with
a Wishbone system-on-a-chip interconnect bridge. The company now has
three different S1 chips, a version with one thread and no L1 caches, a
version with one thread and 24 KB of L1 instruction and data cache, and
a four-thread version with 24 KB of cache. Simply RISC is hoping that
the S1 chip is adopted for mobile phones, PDAs, and other embedded
devices. Taiwanese chip and board maker Polaris Micro has also implemented a single-core variant of the T1.
Hoping
to recreate a little of the magic from its early history twenty years
ago, Sun is focusing on colleges and universities that are in the
process of teaching the next generations of IT experts. Sun was founded
at a major university (Stanford University, in this case), and got
early traction for its products among academics and students--just like
many other IT players today. Having the key textbooks talking about T1
and T3 designs is an important foundation for future business. So is
the opening of five OpenSparc centers of excellence, which the company
also announced in December. The University of California (at Santa
Cruz), the University of Texas, the University of Michigan, the
University of Illinois (at Urbana-Champaign), and Carnegie Mellon
University have all created OpenSparc centers and made a two-year
commitment to do chip design research and coursework based on Sun's
various chip multithreading (CMT) designs.
For
now, that means the current T1 and T2 chips and the future T3 chips. It
should also mean the future "Rock" Sparc RK processors, which will pack
up to 16 cores on a single chip and which will have a radically
different design approach compared to prior UltraSparc chips. If Sun
takes the Sparc RK chip designs open source, it will be a truly
stunning move in the chip and server industries. And given all the
talking that Jonathan Schwartz, Sun's president and chief executive
officer, and the other top brass at Sun have done about open sourcing
all the core technologies at Sun to prove the company is
whole-heartedly behind the open source movement--can anyone say the
word shibboleth?--it seems unlikely that Sun will be able to say it will open source everything but Rock chips.
Only
time will tell if this open source strategy works or not. But no one
can say that Sun is not afraid to bet the farm on a strategy.
Read the original article: http://www.itjungle.com/tlb/tlb010808-story09.html
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