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This week I have been at the International Solid State Circuits
Conference. The big news here has come from several microprocessor
vendors showing off new chips, each of which is designed to advance the
state of the art, but in different ways.
This week I have been at the International Solid State Circuits
Conference. The big news here has come from several microprocessor
vendors showing off new chips, each of which is designed to advance the
state of the art, but in different ways.
Probably
the most attention has gone to Intels discussion of a chip with 80
processing engines, all connected together in a network on chip.
These processor engines or tiles Intel was careful not to use the
word core consists of 2 single-precision floating point units; and
the tiles are connected in an 8 by 10 grid. The idea was to create a
teraflop on a chip, and in particular to get that performance without
using too much power. This chip ended up producing 1.28 Teraflops
of performance while running at 4.27GHz and using 100 watts of power.
Intel
was very clear to point out that this is just a research project to
help figure out the design of future multi-core chips. This
particular chip was highly optimized to run floating point
instructions, but was not designed to run traditional applications.
Still, it points out the direction that most people think the industry
is moving in toward massively parallel chips. The presenter
described it as a building block for peta-scale computing, (For more
details, see ExtremeTechs take here and eWeeks take here.)
Intels
other processor presentation described its Merom chip the Core 2
microprocessor it has been shipping for nearly a year.
In contrast,
other processor makers showed off upcoming chips. One of the most
anticipated was AMDs releasing of new information on Barcelona in
particular, an integrated quad-core version of their server-oriented
Opteron processor. This promises to be the first x86 processor with
four on-die cores; and each core will have 512KB of L2 cache and a
128-bit floating point unit. The chip as a whole has 2MB of shared
Level 3 cache; and can support up to four 16-bit HyperTransport links,
which should allow for 2 to 8 way multiprocessing. The presenter said
the chip has 463 million transistors and is being produced on a 65 nm
process.
Barcelona will be compared with current Xeon
processors that use two dual-core dies in a single package; but should
help AMD be seen as moving to the front of multi-core processing in x86
computing. (For more details, see eWeeks take here.)
But
not to be outdone, both IBM and Sun showed off new processors aimed at
larger servers. IBM showed off its Power6 microprocessor, saying it
doubles the operating frequency of its Power5 chip at the same power,
moving to 4 to more than 5GHz. The 790 million transistor chip
contains 2 cores, each of which has 4MB of level 2 cache. It
includes a decimal floating point processor and a special processor for
multimedia. The chip is designed to provide a total of 300 GB/sec of
total I/0 bandwidth, making it suitable for 128-way SMP systems. It is
expected to be available mid-year.
Sun showed its Niagara 2
SPARC processor, designed to be a low-power system on a chip. This 500
million transistor chip has 8 cores, each running the 64-bit Sparc v9
instruction set, and 4 MB of shared L2 cache. It runs at 1.4GHz at 84
watt.
What does it all mean? TSMC Chairman Morris Chang
opened the conference by noting that the growth rate of the
semiconductor industry has begun to slow down and showed how growth in
the industry averaged 16% per year from 1960 to 2000, but only 6% since
2000. But these developments show that despite that, there are still
plenty of improvements on the horizon.
Read original article: http://blog.pcmag.com/blogs/miller/archive/2007/02/13/1757.aspx
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