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Sun's sequel to Niagara, the appropriately named Niagara2, is going
to be released before long (I hear sometime in April or June), so Sun
gave a good talk on the chip and described it in some detail. Here's an
information dump for the microprocessor geeks in the audience.
Sun's sequel to Niagara, the appropriately named Niagara2, is going
to be released before long (I hear sometime in April or June), so Sun
gave a good talk on the chip and described it in some detail. Here's an
information dump for the microprocessor geeks in the audience.
Niagara2 sports 8 SPARC cores, all of which are connected to 4MB of
shared L2 cache by a large crossbar switch. Each core is capable of
eight-way simultaneous multithreading, giving each Niagra2 chip a total
of 64 simultaneous threads of execution. All of this thread-processing
power enables Niagra2 to double its predecessor's throughput and
performance/watt.
Sun also claims a 10X improvement in floating-point performance over Niagara.
Each SPARC core has a 16K instruction cache and an 8K data cache.
The core's front end fetches 4 instructions per cycle and feeds them
into a back end that consists of the following functional units:
- 1 Load-Store unit
- 2 Integer units
- 1 Floating-point unit
- 1 Cryptographic unit (the "SPU" in Sun's block diagrams)
The two integer units have an 8-stage pipeline with a 3-cycle load-use
latency. The floating-point unit has a 12-stage pipeline (even longer
for division and square root), with a 6-cycle latency for dependant
floating-point operations.
The crypto unit contains a random number generator, and can natively
suppport a number of popular encryption algorithms and hash functions
(RC4, AES, DES, 3DES, SHA-1, and SHA-256). Sun claims that all eight of
these SPUs can be ganged together to provide enough horsepower to run
both of the system's 10 gigabit Ethernet ports fully encrypted at wire
speed.
Speaking of the GigE ports, Niagra2 is an SoC design that sports the
aforementioned two Ethernet ports, an x8 PCIe port, and four
dual-channel FBDIMM controllers.
The 342mm2, 503 million-transistor Niagara2 is fabricated on a 65nm process, and dissipates 84W when running at 1.4GHz.
Read the original article: http://arstechnica.com/news.ars/post/20070213-8826.html
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