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The EEMBC benchmarking
organisation is starting work on a system for comparing multi-processor
core chips, but is at least a year away from a version for embedded
multi-core chips.
The EEMBC benchmarking
organisation is starting work on a system for comparing multi-processor
core chips, but is at least a year away from a version for embedded
multi-core chips.
It is developing a test harness for symmetric
multi-processor (SMP) systems such as the dual and quad core devices
from Intel and AMD.
EEMBC already provides benchmarks tests
for single processors using standard code for different application
areas such as graphics and automotive.
This is the number one
priority in EEMBC right now, to provide a framework to allow people to
run the benchmark on multi-core devices, said Markus Levy, president
of EEMBC, who is also president of the MultiCore Association.
We
are targeting SMP first because its easier and more of the SMP devices
are what people are interested in benchmarking, he said.
With
an SMP model the challenge is finding how to split out the different
threads, but you can run the same coded on each processor with
different data, for example for multiple channels of voice-over-IP,
added Levy.
Embedded multi-core chips such as OMAP from Texas
Instruments or Nomadik from ST Microelectronics use a message passing
interconnect between different cores, which is much harder to test.
How do you write standard C code and distribute that to a number of
different processors and DSPs, said Levy. The MultiCore Association
is developing a common API interface to provide a unified programming
language, and we would like to integrate that into the test harness.
It is thought the SMP version will be ready around the third quarter of next year, with the embedded version coming afterwards.
Read the original article: http://www.electronicsweekly.com/Articles/2006/10/18/39959/Industry+to+get+multi-processor+core+benchmarks.htm
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