Home Get Informed Processor News 2006-09 Oceania: Ex-ST Engineers Release Free RISC Core

Oceania: Ex-ST Engineers Release Free RISC Core

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Written by Jessica Davis (Oceania)   
Wednesday, 13 September 2006 16:00

A group of former STMicroelectronics engineers calling themselves Simply RISC have released the S1 Core, a 64-bit Wishbone-compliant CPU core based on the OpenSPARC T1 microprocessor released by Sun Microsystems a few months ago.

The design is targeting embedded devices such as PDAs, set-top boxes and digital cameras.

Simply RISC is offering the core for free under the same license of the TI, the GNU General Public License (GPL), according to the group's web site. The core is downloadable Simply RISC's site http://www.srisc.com/?home.

A group of former STMicroelectronics engineers calling themselves Simply RISC have released the S1 Core, a 64-bit Wishbone-compliant CPU core based on the OpenSPARC T1 microprocessor released by Sun Microsystems a few months ago.

The design is targeting embedded devices such as PDAs, set-top boxes and digital cameras.

Simply RISC is offering the core for free under the same license of the TI, the GNU General Public License (GPL), according to the group's web site. The core is downloadable Simply RISC's site http://www.srisc.com/?home.

The environment can run on any Unix/Linux box and requires no commercial tools, since both simulation and synthesis of the Verilog files of the design can be performed using the free software, Icarus Verilog, the organization said.

Simply RISC said it plans to add new features to the core and test them over the next few months with the help of the open source community.

The core's Wishbone-compliant bus interface enables easy interconnection to several cores that are freely available on OpenCores.org to build systems-on-chip.

The Simply RISC team has been working in Catania, Italy and Bristol, UK to develop and support CPU cores, peripherals and interfaces released under the GNU General Public License to build up free hardware design of microprocessors, Systems-on-a-Chip (SoC) and Networks-on-a-Chip (NoC).

Future designs, such as SoCs and peripherals, will be publicly released on Simply RISC's site, on OpenSPARC.net and on OpenCores.org.

 

Read the original article: http://oceania.digitalmedianet.com/articles/viewarticle.jsp?id=65867

 
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