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Simply RISC, a team of engineers formerly with
STMicroelectronics NV who have been working in Catania, Italy and
Bristol, England, has produced its first offering, a 64-bit processor
codednamed Sirocco and now dubbed the S1 core.
It is not clear what business model Simply RISC will pursue
as it offers the core for free and free technical support, according to
the Simply RISC website www.srisc.com.
Simply RISC, a team of engineers formerly with
STMicroelectronics NV who have been working in Catania, Italy and
Bristol, England, has produced its first offering, a 64-bit processor
codednamed Sirocco and now dubbed the S1 core.
It is not clear what business model Simply RISC will pursue
as it offers the core for free and free technical support, according to
the Simply RISC website www.srisc.com.
"Simply RISC develops and supports CPU cores, peripherals and
interfaces released under the GNU General Public License (GPL) to build
up free hardware design of microprocessors, Systems-on-a-Chip (SoC) and
Networks-on-a-Chip (NoC)," the team said on the website.
The S1 is a "cut-down" version of the OpenSPARC T1
multiprocessor, previously codenamed Niagara that targets embedded
devices such as PDAs, set-top boxes and digital cameras.
The OpenSPARC T1 multiprocessor has been released under the GPL license
and features eight SPARC CPU Cores and several peripherals, Simply RISC
said on their website. The S1 takes one of the 64-bit SPARC cores from
that design and adds a "Wishbone" bridge, a reset controller and a
basic interrupt controller, to make it easy for a system engineer to
integrate the design with other cores. Wishbone is an on-chip bus
standard developed with the open hardware community.
As a derivative of the OpenSPARC T1, the S1 retains the ability to
execute four concurrent threads at the same time; and operating systems
support for OpenSolaris and GNU/Linux distributions, such as Ubuntu and
Gentoo, which will detect four different CPUs even if on the chip the
CPU core is only one. Simulation and synthesis of Verilog files which
make upthe S1 design can be done using free software such as Icarus
Verilog, Simply RISC said.
Future designs such as SoCs based on S1 and peripherals for it will be released on the Simply RISC webstie and on www.OpenSPARC.net and on www.OpenCores.org. The OpenCores project has been running as a loose alliance of students and semiprofessional chip developers since 2000.
The open hardware movement is strong in Europe. OpenSoCDesign
(Madrid, Spain) has a distinct advantage. This Spanish startup is
focusing on system development using open-source cores, and is helping
create an infrastructure to make such cores more usable.
The British and Italian origins of Simply RISC has resulted in
the group adopting as its logo a square Union flag but with Italian
colors.
Read the original article: http://www.eetimes.com/news/design/showArticle.jhtml?articleID=193000635
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