EE Times: Free processor firm discloses business plans

Simply RISC, a team of engineers formerly with STMicroelectronics NV, has revealed plans to provide design services around its offering of a free 64-bit processor core. Simply RISC's release of the OpenSPARC T1-based processor is intended to show potential customers the team's capability as well as providing a building block for future system-on-chip and network-on-chip design work.

Simply RISC, a team of engineers formerly with STMicroelectronics NV, has revealed plans to provide design services around its offering of a free 64-bit processor core. Simply RISC's release of the OpenSPARC T1-based processor is intended to show potential customers the team's capability as well as providing a building block for future system-on-chip and network-on-chip design work.

"Simply RISC is a design center. We haven't plans to sell chips. What we can offer is our time and our expertise," said Fabrizio Fazzino, who described himself as chief system architect, in an email to EE Times. Fazzino went on to say that companies can come to Simply RISC to develop SoC and NoC integrated circuits using either ASIC or field-programmable gate array implementation. "The IP cores we develop are fully released under the GPL, unless a customer asks us to do otherwise," Fazzino added referring to the GNU General Public License.

The S1 is a "cut-down" version of the OpenSPARC T1 multiprocessor, previously codenamed Niagara, which targets embedded devices such as PDAs, set-top boxes and digital cameras. The S1 comprises a single four-thread processor core, rather than the eight four-thread cores present on the T1. However, it is still early days for Simply RISC, which is seeking funding and comprises just five engineers at present.

Fazzino himself worked for ST in Catania, Sicily, between 1998 and 2001 in the group which developed the ST20 and ST40 processors. The group was formed as a result of the acquisition, in 1989 of Inmos Ltd., a U.K. semiconductor company based in Bristol, England, and well-known for having developed a parallel processor known as the transputer.

Fazzino decided to leave ST in 2001 to become a free-lance chip designer, but with the idea to found a company with some former colleagues. "We are all Italian and we work in Italy. However, we are receiving many contacts from all over the world from people who want to help, especially from India and China," said Fazzino. "I would like to include also them in the head count and I probably will in the future."

Fazzino said that the original intention was for Simply RISC to develop its own simple RISC processor targeted towards small embedded devices. However, the company changed tack and opted to develop an OpenSPARC-derivative processor.

Following in Gaisler's footsteps

Simply RISC is not inclined to develop SoCs and NoCs for customers around other processor cores, such as ARM, MIPS or ARC, according to Fazzino. He said it would be better for Simply RISC to focus on the S1 and T1 as the team has gained a lot of knowledge and expertise around the architecture in recent months. Simply RISC engineers served as beta testers for the OpenSPARC T1 processor prior to its official launch, he added.

"We will see how the OpenSPARC community evolves, especially if Sun releases the next version of their state-of-the-art microprocessor. If Sun will publicly release a T2 there will probably be an S2 core," said Fazzino, when asked about road-map for processor core development.

As a derivative of the T1, the S1 is already well set to support multiprocessing. The S1 retains the ability to execute four concurrent threads at the same time; and provides operating systems support for OpenSolaris and GNU/Linux distributions, such as Ubuntu and Gentoo, which will detect four different CPUs even if on the chip the CPU core is only one.

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