The
new chip is seen as an ideal embedded chip product that can be used in
handheld computers, set-top boxes and digital cameras.
The S1
Core is released under the same licence of the T1, the GNU General
Public Licence (GPL), and the design is freely downloadable from the
Simply RISC website at www.srisc.com, with no registration required.
One
of the main aims of Simply RISC was to keep the S1 Core environment as
simple as possible to encourage developers. Most of the simulation and
synthesis activities are now performed with simple push-button scripts
and system requirements are very easy to meet, said Simply RISC.
The
environment can run on any Unix/Linux box and no commercial tools are
required, since both simulation and synthesis of the Verilog files of
the design can be performed using the free software Icarus Verilog.
Due
to its Wishbone-compliant bus interface the S1 Core can be easily
interconnected to several cores freely available on OpenCores.org to
build up a System-on-a-Chip.
With the collaborative nature of
the GPL licence, Simply RISC plans to add new features to the S1 Core
and test them extensively over the next few months with the help of the
open-source community.