OpenSPARC on FPGA

OpenSPARC T1 release 1.6 now supports:

• T1 core supports single- and four-thread options on FPGAs
• Reference designs boot OpenSolaris on single- or four-thread mode
• Xilinx Virtex-5 technology support
• Networking (ftp, telnet) support

These new features are designed to enable a user to build real systems using the OpenSPARC T1 core.

If you are a professor you can apply for an OpenSPARC Evaluation Platform through our OpenSPARC University Program.

One can also order OpenSPARC Evaluation Platform directly from Digilent. For pricing and ordering information, go to Digilent.

Here is a video demonstrating OpenSPARC T1 running on the Xilinx Virtex 4 FPGA board.

This presentation (updated for release 1.6 on July 3, 2008) is a Tutorial on using OpenSPARC T1 in an FPGA, "OpenSPARC T1 FPGA Implementation"

Join the OpenSPARC FPGA project
The FPGA Project intent is to allow FPGA implementation experts to take what was provided with the latest OpenSPARC T1 release and to further develop the FPGA implementation including work to optimize area and timing of this design and contribute their changes back to this project and to shared with the community.  Contribute the project or just tell us what you have done.  Initial join as an observer and with your contributions your role (and responsibility) will be increased.

More Information

• Sun and Xilinx Unveil FPGA Board
• Update from RAMP Retreat, August 2008 - Shown is how two and four boards can be interconnected to build a multi-core OpenSPARC T1.  
• Gaisler Research: GRLIB - The GRLIB IP Library is an integrated set of reusable IPcores, designed for system-on-chip (SOC) development. The IP cores are centered around a common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug & play method is used to configure and connect the IP cores without the need to modify any global resources.