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Oracle OpenWorld 2010: Sept. 20-24, 2010

2010-09-19T17:30:31Z

Oracle Unveils SPARC T3 Systems

http://www.oracle.com/us/corporate/features/sparc-t3-feature-173454.html

Watch all the keynotes from Oracle OpenWorld, JavaOne, and Oracle Develop Live:

http://www.oracle.com/us/openworld

HOTCHIPS21: Sun's Next-Generation Multi-threaded Processor - Rainbow Falls

2009-08-25T17:00:00Z

Abstract: Presentation made at the HOT CHIPS 21, on August 23-25, 2009, Stanford, CA.

Authors: Sanjay Patel, Stephen Phillips and Allan Strong

Presentation: 'Sun's Next-Generation Multi-threaded Processor - Rainbow Falls'

HOTCHIPS21: Sun's 3rd generation on-chip UltraSPARC security accelerator

2009-08-25T17:00:00Z

Abstract: Presentation made at the HOT CHIPS 21, on August 23-25, 2009, Stanford, CA.

Author:Lawrence Spracklen

Presentation: 'Sun's 3rd generation on-chip UltraSPARC security accelerator '

OpenSPARC T2 HW 1.3 Released

2009-07-28T15:06:40Z

UltraSPARC T2 - Click to enlarge

The OpenSPARC T2 processor is based on the UltraSPARC T2 processor, the world's fastest commodity processor with eight cores and eight threads per core.

In HW release 1.3, a fully synthesizable, reduced footprint, System-level model has been developed, suitable for FPGA and Emulation Platforms. This model has single OpenSPARC T2 core, crossbar interconnect, and WISHBONE Memory Controller ( from www.opencores.org). This environment supports RTL Simulation, FPGA Synthesis and Gate-level simulation with a one-to-one correspondence (i.e a given test runs unchanged in the RTL & Gate environments.) This environment is hardware platform neutral and can be ported on any FPGA prototyping board.

The software tools portion of the download is at release 1.2.

Read more for new features in HW release 1.3 and SW release 1.2

Download HW 1.3 and SW Release 1.2 and OpenSPARC T2 specifications

Synthesizing OpenSPARC design using Synopsys 90nm Technology Library

2009-04-27T23:52:18Z

This course is created by Synopsys Inc. and is made available from the Synopsys University Program. This package includes design, documentation, and scripts to synthesize OpenSPARC T1 Floating-Point Unit (FPU) using Synopsys Inc, Electronic Design Automation (EDA) tools. Primary goal of this package is to provide students sand-box environment within which they can learn and apply logic synthesis concepts on a real world design example.

This lab requires the following software and libraries:

Synopsys Design Compiler version B-2008.09 or later
Synopsys 90nm generic library
OpenSPARC T1 version 1.6 or later
Synopsys supported Compute Platform

OpenSPARC T1 HW 1.7 Released

2009-04-09T18:00:00Z

New Features in the HW Release 1.7 of OpenSPARC T1

More Xilinx FPGA support for Virtex 5 FPGAs
Support for a dual-core system using two OpenSPARC development boards
Support for Ubuntu Linux boot
Support for BEE3
Improved CCX Firmware code
Improved performance when running regressions of diagnostic tests

For details read more...

Download HW 1.7 and SW 1.5 and OpenSPARC T1 Specfications

Nangate 45nm Open Cell Library supports OpenSPARC

2009-02-17T21:44:06Z

Nangate and Sun Microsystems, Inc. are delighted to announce the interoperability of industry leading open-source 64-bit Chip Multi-threading (CMT) microprocessor design by Sun with Nangate's 45nm Open Cell Library.

Users can now synthesize and optimize state-of-the-art OpenSPARC T1 and OpenSPARC T2 design blocks, using industry standard synthesis tools, on a 45nm technology supplied by Nangate. We believe this combination will facilitate research and experimentation in modern VLSI design topics like timing and noise, reliability, and process variation among other things. We also believe the open-source nature of these two offerings will allow researchers to modify and test new ideas in a consistent and reproducible manner.

European Universities Join OpenSPARC

2008-11-05T14:00:00Z

Sun Microsystems, Inc. and Europractice today announced a three-year collaboration to promote OpenSPARC CMT (Chip Multithreading) technology -- one of the only open sourced multi-core, multithreaded processor architectures--as a reference design among 650 universities and research institutions across 38 countries in the European region. Europractice is a European Union-backed non-profit microelectronics design stimulation project managed by the STFC Rutherford Appleton Laboratory.

Sun and Xilinx Unveil FPGA Board

2008-09-07T19:08:33Z

At the International Conference for Field Programmable Logic and Applications today, Sun Microsystems, Inc. and Xilinx, Inc. unveiled a feature-rich, high-performance programmable OpenSPARC evaluation platform. The platform provides academic researchers and hardware developers with a flexible OpenSPARC-based platform to create, customize and deploy next-generation applications for a broad set of end markets including supercomputers, industrial, scientific and medical (ISM), aerospace & defense, and storage and networking.

"Our collaboration with industry leaders such as Xilinx will continue to drive the momentum and expansion of the UltraSPARC ecosystem," said Mike Knudsen, vice president, business development and marketing for Sun's Microelectronics unit. "The microprocessor industry is steadily shifting towards CMT architectures, and this new OpenSPARC FPGA evaluation platform puts us in a prime position to enable faster time-to-market for our customers."

OpenSPARC Centers of Excellence

2007-12-07T17:46:17Z

Ten major universities are now official OpenSPARC Technology Centers of Excellence:

University of California, Santa Cruz, USA
University of Texas, Austin, USA
University of Michigan, Ann Arbor
University of Illinois, Urbana-Champaign, USA
Carnegie Mellon University, USA
Stanford University, USA
University of Otago, Dunedin, New Zealand
Peking University, China
Tsinghua University, China
University of Sao Paulo, Brazil

Each Center of Excellence has a minimum two-year commitment, during which time they'll execute chip design research and course work based on Sun's chip multi-threading (CMT) design.

Visit our Centers of Excellence web page.